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drm/i915: mask the video DIP frequency when changing it 

Better safe than sorry. Currently we never change the frequency and
use the same for every infoframe type, so the only way to reproduce a
bug would be with the BIOS doing something.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Paulo Zanoni 2012-05-04 17:18:22 -03:00 committed by Daniel Vetter
parent ecb978515c
commit 60c5ea2dd9
2 changed files with 4 additions and 0 deletions
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1
drivers/gpu/drm/i915/i915_reg.h
View File

@ -1711,6 +1711,7 @@
#define VIDEO_DIP_FREQ_ONCE (0 << 16)
#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
#define VIDEO_DIP_FREQ_MASK (3 << 16)
/* Panel power sequencing */
#define PP_STATUS 0x61200

3
drivers/gpu/drm/i915/intel_hdmi.c
View File

@ -164,6 +164,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder,
}
val |= intel_infoframe_enable(frame);
val &= ~VIDEO_DIP_FREQ_MASK;
val |= intel_infoframe_frequency(frame);
I915_WRITE(VIDEO_DIP_CTL, val);
@ -203,6 +204,7 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder,
}
val |= intel_infoframe_enable(frame);
val &= ~VIDEO_DIP_FREQ_MASK;
val |= intel_infoframe_frequency(frame);
I915_WRITE(reg, val);
@ -236,6 +238,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
}
val |= intel_infoframe_enable(frame);
val &= ~VIDEO_DIP_FREQ_MASK;
val |= intel_infoframe_frequency(frame);
I915_WRITE(reg, val);