mirror of https://gitee.com/openkylin/linux.git
drm/amd/powerplay: support UMD PSTATE settings on arcturus
Enable arcturus UMD PSTATE support. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan
Alex Deucher
parent
4bf76e60b9
commit
60d435b73d
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@ -664,15 +664,15 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
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}
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static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
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uint32_t feature_mask)
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uint32_t feature_mask)
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{
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struct arcturus_dpm_table *dpm_table;
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struct arcturus_single_dpm_table *single_dpm_table;
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struct arcturus_dpm_table *dpm_table =
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smu->smu_dpm.dpm_context;
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uint32_t freq;
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int ret = 0;
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dpm_table = smu->smu_dpm.dpm_context;
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if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT) &&
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if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
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(feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
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single_dpm_table = &(dpm_table->gfx_table);
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freq = max ? single_dpm_table->dpm_state.soft_max_level :
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@ -687,6 +687,36 @@ static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
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}
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}
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if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
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(feature_mask & FEATURE_DPM_UCLK_MASK)) {
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single_dpm_table = &(dpm_table->mem_table);
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freq = max ? single_dpm_table->dpm_state.soft_max_level :
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single_dpm_table->dpm_state.soft_min_level;
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ret = smu_send_smc_msg_with_param(smu,
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(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
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(PPCLK_UCLK << 16) | (freq & 0xffff));
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if (ret) {
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pr_err("Failed to set soft %s memclk !\n",
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max ? "max" : "min");
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return ret;
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}
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}
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if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
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(feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
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single_dpm_table = &(dpm_table->soc_table);
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freq = max ? single_dpm_table->dpm_state.soft_max_level :
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single_dpm_table->dpm_state.soft_min_level;
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ret = smu_send_smc_msg_with_param(smu,
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(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
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(PPCLK_SOCCLK << 16) | (freq & 0xffff));
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if (ret) {
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pr_err("Failed to set soft %s socclk !\n",
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max ? "max" : "min");
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return ret;
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}
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}
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return ret;
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}
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@ -1086,6 +1116,194 @@ static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
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return ret;
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}
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static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
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{
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uint32_t i;
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for (i = 0; i < table->count; i++) {
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if (table->dpm_levels[i].enabled)
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break;
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}
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if (i >= table->count) {
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i = 0;
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table->dpm_levels[i].enabled = true;
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}
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return i;
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}
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static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table)
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{
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int i = 0;
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if (table->count <= 0) {
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pr_err("[%s] DPM Table has no entry!", __func__);
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return 0;
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}
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if (table->count > MAX_DPM_NUMBER) {
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pr_err("[%s] DPM Table has too many entries!", __func__);
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return MAX_DPM_NUMBER - 1;
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}
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for (i = table->count - 1; i >= 0; i--) {
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if (table->dpm_levels[i].enabled)
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break;
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}
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if (i < 0) {
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i = 0;
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table->dpm_levels[i].enabled = true;
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}
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return i;
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}
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static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
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{
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struct arcturus_dpm_table *dpm_table =
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(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
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uint32_t soft_level;
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int ret = 0;
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/* gfxclk */
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if (highest)
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soft_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
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else
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soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
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dpm_table->gfx_table.dpm_state.soft_min_level =
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dpm_table->gfx_table.dpm_state.soft_max_level =
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dpm_table->gfx_table.dpm_levels[soft_level].value;
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/* uclk */
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if (highest)
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soft_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
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else
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soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
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dpm_table->mem_table.dpm_state.soft_min_level =
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dpm_table->mem_table.dpm_state.soft_max_level =
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dpm_table->mem_table.dpm_levels[soft_level].value;
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/* socclk */
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if (highest)
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soft_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
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else
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soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
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dpm_table->soc_table.dpm_state.soft_min_level =
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dpm_table->soc_table.dpm_state.soft_max_level =
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dpm_table->soc_table.dpm_levels[soft_level].value;
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ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
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if (ret) {
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pr_err("Failed to upload boot level to %s!\n",
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highest ? "highest" : "lowest");
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return ret;
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}
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ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
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if (ret) {
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pr_err("Failed to upload dpm max level to %s!\n!",
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highest ? "highest" : "lowest");
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return ret;
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}
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return ret;
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}
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static int arcturus_unforce_dpm_levels(struct smu_context *smu)
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{
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struct arcturus_dpm_table *dpm_table =
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(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
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uint32_t soft_min_level, soft_max_level;
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int ret = 0;
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/* gfxclk */
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soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
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soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
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dpm_table->gfx_table.dpm_state.soft_min_level =
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dpm_table->gfx_table.dpm_levels[soft_min_level].value;
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dpm_table->gfx_table.dpm_state.soft_max_level =
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dpm_table->gfx_table.dpm_levels[soft_max_level].value;
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/* uclk */
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soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
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soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
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dpm_table->mem_table.dpm_state.soft_min_level =
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dpm_table->gfx_table.dpm_levels[soft_min_level].value;
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dpm_table->mem_table.dpm_state.soft_max_level =
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dpm_table->gfx_table.dpm_levels[soft_max_level].value;
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/* socclk */
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soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
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soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
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dpm_table->soc_table.dpm_state.soft_min_level =
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dpm_table->soc_table.dpm_levels[soft_min_level].value;
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dpm_table->soc_table.dpm_state.soft_max_level =
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dpm_table->soc_table.dpm_levels[soft_max_level].value;
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ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
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if (ret) {
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pr_err("Failed to upload DPM Bootup Levels!");
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return ret;
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}
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ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
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if (ret) {
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pr_err("Failed to upload DPM Max Levels!");
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return ret;
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}
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return ret;
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}
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static int
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arcturus_get_profiling_clk_mask(struct smu_context *smu,
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enum amd_dpm_forced_level level,
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uint32_t *sclk_mask,
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uint32_t *mclk_mask,
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uint32_t *soc_mask)
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{
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struct arcturus_dpm_table *dpm_table =
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(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
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struct arcturus_single_dpm_table *gfx_dpm_table;
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struct arcturus_single_dpm_table *mem_dpm_table;
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struct arcturus_single_dpm_table *soc_dpm_table;
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if (!smu->smu_dpm.dpm_context)
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return -EINVAL;
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gfx_dpm_table = &dpm_table->gfx_table;
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mem_dpm_table = &dpm_table->mem_table;
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soc_dpm_table = &dpm_table->soc_table;
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*sclk_mask = 0;
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*mclk_mask = 0;
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*soc_mask = 0;
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if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
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mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
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soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
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*sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
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*mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
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*soc_mask = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
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}
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if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
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*sclk_mask = 0;
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} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
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*mclk_mask = 0;
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} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
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*sclk_mask = gfx_dpm_table->count - 1;
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*mclk_mask = mem_dpm_table->count - 1;
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*soc_mask = soc_dpm_table->count - 1;
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}
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return 0;
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}
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static void arcturus_dump_pptable(struct smu_context *smu)
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{
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struct smu_table_context *table_context = &smu->smu_table;
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@ -1546,6 +1764,9 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
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.read_sensor = arcturus_read_sensor,
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.get_fan_speed_percent = arcturus_get_fan_speed_percent,
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.get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
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.force_dpm_limit_value = arcturus_force_dpm_limit_value,
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.unforce_dpm_levels = arcturus_unforce_dpm_levels,
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.get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
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/* debug (internal used) */
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.dump_pptable = arcturus_dump_pptable,
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};
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