mirror of https://gitee.com/openkylin/linux.git
Second Round of Renesas ARM Based SoC DT Timers Updates for v3.18
* kzm9g-reference: Enable CMT1 in device tree * Use SoC-specific timer compat strings -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUEPAEAAoJENfPZGlqN0++GX0P/in7JxaEeSH1f1PRV6mWSJAH C9hEx7nlD0DfWttuZ+viurKL7GNdLiASXXb3188KmxY4SDUnG77o1qChhzyFXP6Z 2FyCwSafunI+6pVB+zuPzRQRtn52qZOvU0sANPvwh6Cz3GUtUqw2ojxXo/gPo393 020938zFzaghhDYN2OpV2I+IC6yAgUycwEZCHFNMLoTJh95FQhbwbJBs7zIbYovE 8RpTdj2Y3uQe1ATf/WDWGfVuwfRiHgIQJmqkaQmCfIAZiQ0xH6qUCGUza+Pz4l8z 9t9zBpPuaaIppg73+fga9UuI6BTCxzwz2Wv3NnAnbIsVPrQCx1hVnz6DPYjXwphK fENryV8I16xkniceQYLvalpeRK/btGeUEhuB+pvsuhE/+IECfOmYKgm4lXG8wB4h P0v1zMVy2OSNMI6uSDVoKLEH2U6i9J9ow4jarXkBvbG8Duk6CbUXKGNud9RnEswK Z6e7fRTh80puhh8TCo5f+9CbtVS47fCA62gy/L3bMQxddlt3XR5KJ5IIDASwaCcM mjFvOrXF4kMcegyYhVGcqYwG8CdSm+4Ymeevfk4F2KaxIZ4Wh69/J2dCTsiLYJvJ VRIGfEpjO8aqN1lY1A4j+y89byn0O03I7XuMUSmESyz+19HvC/EvGZpR3hggBLrD +TFSXHvGA7RbNik+ilLY =SogR -----END PGP SIGNATURE----- Merge tag 'renesas-dt-timers2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Pull "Second Round of Renesas ARM Based SoC DT Timers Updates for v3.18" from Simon Horman: * kzm9g-reference: Enable CMT1 in device tree * Use SoC-specific timer compat strings Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'renesas-dt-timers2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: kzm9g-reference: Enable CMT1 in device tree ARM: shmobile: sh73a0: Add CMT1 device to DT ARM: shmobile: r8a7740: Use SoC-specific 48-bit CMT compat string ARM: shmobile: r8a7779: Use SoC-specific TMU compat string ARM: shmobile: r8a7791: Use SoC-specific 48-bit CMT compat string ARM: shmobile: r7s72100: Use SoC-specific MTU2 compat string ARM: shmobile: r8a7790: Use SoC-specific 48-bit CMT compat string
This commit is contained in:
commit
60f91268ee
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@ -230,7 +230,7 @@ i2c3: i2c@fcfeec00 {
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};
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mtu2: timer@fcff0000 {
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compatible = "renesas,mtu2";
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compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
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reg = <0xfcff0000 0x400>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tgi0a";
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@ -42,7 +42,7 @@ pmu {
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};
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cmt1: timer@e6138000 {
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compatible = "renesas,cmt-48";
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compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
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reg = <0xe6138000 0x170>;
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interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
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@ -267,7 +267,7 @@ thermal@ffc48000 {
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};
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tmu0: timer@ffd80000 {
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compatible = "renesas,tmu";
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compatible = "renesas,tmu-r8a7779", "renesas,tmu";
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reg = <0xffd80000 0x30>;
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interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
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<0 33 IRQ_TYPE_LEVEL_HIGH>,
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@ -281,7 +281,7 @@ tmu0: timer@ffd80000 {
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};
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tmu1: timer@ffd81000 {
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compatible = "renesas,tmu";
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compatible = "renesas,tmu-r8a7779", "renesas,tmu";
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reg = <0xffd81000 0x30>;
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interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
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<0 37 IRQ_TYPE_LEVEL_HIGH>,
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@ -295,7 +295,7 @@ tmu1: timer@ffd81000 {
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};
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tmu2: timer@ffd82000 {
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compatible = "renesas,tmu";
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compatible = "renesas,tmu-r8a7779", "renesas,tmu";
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reg = <0xffd82000 0x30>;
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interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
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<0 41 IRQ_TYPE_LEVEL_HIGH>,
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@ -207,7 +207,7 @@ timer {
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};
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cmt0: timer@ffca0000 {
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compatible = "renesas,cmt-48-gen2";
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compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
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reg = <0 0xffca0000 0 0x1004>;
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interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
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<0 143 IRQ_TYPE_LEVEL_HIGH>;
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@ -220,7 +220,7 @@ cmt0: timer@ffca0000 {
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};
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cmt1: timer@e6130000 {
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compatible = "renesas,cmt-48-gen2";
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compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
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reg = <0 0xe6130000 0 0x1004>;
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interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
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<0 121 IRQ_TYPE_LEVEL_HIGH>,
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@ -190,7 +190,7 @@ timer {
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};
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cmt0: timer@ffca0000 {
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compatible = "renesas,cmt-48-gen2";
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compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
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reg = <0 0xffca0000 0 0x1004>;
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interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
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<0 143 IRQ_TYPE_LEVEL_HIGH>;
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@ -203,7 +203,7 @@ cmt0: timer@ffca0000 {
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};
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cmt1: timer@e6130000 {
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compatible = "renesas,cmt-48-gen2";
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compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
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reg = <0 0xe6130000 0 0x1004>;
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interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
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<0 121 IRQ_TYPE_LEVEL_HIGH>,
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@ -173,6 +173,10 @@ simple-audio-card,codec {
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};
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};
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&cmt1 {
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status = "ok";
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};
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&i2c0 {
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status = "okay";
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as3711@40 {
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@ -47,6 +47,16 @@ pmu {
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<0 56 IRQ_TYPE_LEVEL_HIGH>;
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};
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cmt1: timer@e6138000 {
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compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
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reg = <0xe6138000 0x200>;
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interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
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renesas,channels-mask = <0x3f>;
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status = "disabled";
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};
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irqpin0: irqpin@e6900000 {
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compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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@ -697,10 +697,6 @@ static struct platform_device irqpin3_device = {
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},
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};
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static struct platform_device *sh73a0_devices_dt[] __initdata = {
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&cmt1_device,
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};
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static struct platform_device *sh73a0_early_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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@ -713,6 +709,7 @@ static struct platform_device *sh73a0_early_devices[] __initdata = {
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&scif8_device,
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&tmu0_device,
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&ipmmu_device,
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&cmt1_device,
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};
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static struct platform_device *sh73a0_late_devices[] __initdata = {
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@ -737,8 +734,6 @@ void __init sh73a0_add_standard_devices(void)
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/* Clear software reset bit on SY-DMAC module */
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__raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
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platform_add_devices(sh73a0_devices_dt,
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ARRAY_SIZE(sh73a0_devices_dt));
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platform_add_devices(sh73a0_early_devices,
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ARRAY_SIZE(sh73a0_early_devices));
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platform_add_devices(sh73a0_late_devices,
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@ -763,8 +758,6 @@ void __init sh73a0_earlytimer_init(void)
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void __init sh73a0_add_early_devices(void)
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{
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early_platform_add_devices(sh73a0_devices_dt,
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ARRAY_SIZE(sh73a0_devices_dt));
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early_platform_add_devices(sh73a0_early_devices,
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ARRAY_SIZE(sh73a0_early_devices));
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@ -779,8 +772,6 @@ void __init sh73a0_add_standard_devices_dt(void)
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/* clocks are setup late during boot in the case of DT */
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sh73a0_clock_init();
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platform_add_devices(sh73a0_devices_dt,
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ARRAY_SIZE(sh73a0_devices_dt));
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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