mirror of https://gitee.com/openkylin/linux.git
Merge branch 'clk-pr-err' into clk-next
* clk-pr-err: clk: h8300: pr_err() strings should end with newlines clk: h8s2678: pr_err() strings should end with newlines SPEAr: clk: pr_err() strings should end with newlines clk: SPEAr: pr_err() strings should end with newlines clk: lpc32xx: pr_err() strings should end with newlines clk: stm32f4: pr_err() strings should end with newlines
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commit
617e534dc0
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@ -1424,7 +1424,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
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base = of_iomap(np, 0);
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if (!base) {
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pr_err("%s: unable to map resource", np->name);
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pr_err("%s: unable to map resource\n", np->name);
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return;
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}
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@ -24,13 +24,13 @@ static void __init h8300_div_clk_setup(struct device_node *node)
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num_parents = of_clk_get_parent_count(node);
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if (!num_parents) {
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pr_err("%s: no parent found", clk_name);
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pr_err("%s: no parent found\n", clk_name);
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return;
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}
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divcr = of_iomap(node, 0);
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if (divcr == NULL) {
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pr_err("%s: failed to map divide register", clk_name);
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pr_err("%s: failed to map divide register\n", clk_name);
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goto error;
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}
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offset = (unsigned long)divcr & 3;
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@ -93,7 +93,7 @@ static void __init h8s2678_pll_clk_setup(struct device_node *node)
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num_parents = of_clk_get_parent_count(node);
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if (!num_parents) {
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pr_err("%s: no parent found", clk_name);
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pr_err("%s: no parent found\n", clk_name);
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return;
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}
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@ -104,13 +104,13 @@ static void __init h8s2678_pll_clk_setup(struct device_node *node)
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pll_clock->sckcr = of_iomap(node, 0);
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if (pll_clock->sckcr == NULL) {
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pr_err("%s: failed to map divide register", clk_name);
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pr_err("%s: failed to map divide register\n", clk_name);
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goto free_clock;
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}
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pll_clock->pllcr = of_iomap(node, 1);
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if (pll_clock->pllcr == NULL) {
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pr_err("%s: failed to map multiply register", clk_name);
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pr_err("%s: failed to map multiply register\n", clk_name);
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goto unmap_sckcr;
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}
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@ -526,7 +526,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
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!(pll_is_valid(parent_rate, 1, 1000000, 20000000)
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&& pll_is_valid(cco_rate, 1, 156000000, 320000000)
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&& pll_is_valid(ref_rate, 1, 1000000, 27000000)))
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pr_err("%s: PLL clocks are not in valid ranges: %lu/%lu/%lu",
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pr_err("%s: PLL clocks are not in valid ranges: %lu/%lu/%lu\n",
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clk_hw_get_name(hw),
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parent_rate, cco_rate, ref_rate);
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@ -1505,7 +1505,7 @@ static void __init lpc32xx_clk_init(struct device_node *np)
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return;
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}
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if (clk_get_rate(clk_32k) != 32768) {
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pr_err("invalid clock rate of external 32KHz oscillator");
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pr_err("invalid clock rate of external 32KHz oscillator\n");
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return;
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}
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@ -131,7 +131,7 @@ struct clk *clk_register_frac(const char *name, const char *parent_name,
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struct clk *clk;
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if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
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pr_err("Invalid arguments passed");
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pr_err("Invalid arguments passed\n");
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return ERR_PTR(-EINVAL);
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}
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@ -120,7 +120,7 @@ struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
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struct clk *clk;
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if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
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pr_err("Invalid arguments passed");
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pr_err("Invalid arguments passed\n");
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return ERR_PTR(-EINVAL);
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}
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