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drm/msm/mdp5: don't pre-reserve LM's if no dual-dsi 

If there is only a single DSI interface, don't reserve the first two
layer-mixers for the dual-DSI use-case.

This was causing problems for WB, not being able to assign a LM, on
8x16, which has only two LM's and a single DSI.

Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark 2018-02-19 08:31:29 -05:00
parent 583c13fd77
commit 61b734cb7c
1 changed files with 5 additions and 1 deletions
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6
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
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@ -691,6 +691,7 @@ struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,
struct mdp5_ctl_manager *ctl_mgr; struct mdp5_ctl_manager *ctl_mgr;
const struct mdp5_cfg_hw *hw_cfg = mdp5_cfg_get_hw_config(cfg_hnd); const struct mdp5_cfg_hw *hw_cfg = mdp5_cfg_get_hw_config(cfg_hnd);
int rev = mdp5_cfg_get_hw_rev(cfg_hnd); int rev = mdp5_cfg_get_hw_rev(cfg_hnd);
unsigned dsi_cnt = 0;
const struct mdp5_ctl_block *ctl_cfg = &hw_cfg->ctl; const struct mdp5_ctl_block *ctl_cfg = &hw_cfg->ctl;
unsigned long flags; unsigned long flags;
int c, ret; int c, ret;
@ -740,7 +741,10 @@ struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,
* only write into CTL0's FLUSH register) to keep two DSI pipes in sync. * only write into CTL0's FLUSH register) to keep two DSI pipes in sync.
* Single FLUSH is supported from hw rev v3.0. * Single FLUSH is supported from hw rev v3.0.
*/ */
if (rev >= 3) { for (c = 0; c < ARRAY_SIZE(hw_cfg->intf.connect); c++)
if (hw_cfg->intf.connect[c] == INTF_DSI)
dsi_cnt++;
if ((rev >= 3) && (dsi_cnt > 1)) {
ctl_mgr->single_flush_supported = true; ctl_mgr->single_flush_supported = true;
/* Reserve CTL0/1 for INTF1/2 */ /* Reserve CTL0/1 for INTF1/2 */
ctl_mgr->ctls[0].status |= CTL_STAT_BOOKED; ctl_mgr->ctls[0].status |= CTL_STAT_BOOKED;