mirror of https://gitee.com/openkylin/linux.git
drm/radeon/dpm: add helpers for extended power tables (v2)
This data will be needed for dpm on newer asics. v2: fix typo in rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
8a227555a8
commit
61b7d60110
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@ -721,3 +721,182 @@ bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor)
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return false;
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}
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}
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union power_info {
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struct _ATOM_POWERPLAY_INFO info;
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struct _ATOM_POWERPLAY_INFO_V2 info_2;
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struct _ATOM_POWERPLAY_INFO_V3 info_3;
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struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
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struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
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struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
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struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
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struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
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};
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union fan_info {
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struct _ATOM_PPLIB_FANTABLE fan;
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struct _ATOM_PPLIB_FANTABLE2 fan2;
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};
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static int r600_parse_clk_voltage_dep_table(struct radeon_clock_voltage_dependency_table *radeon_table,
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ATOM_PPLIB_Clock_Voltage_Dependency_Table *atom_table)
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{
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u32 size = atom_table->ucNumEntries *
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sizeof(struct radeon_clock_voltage_dependency_entry);
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int i;
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radeon_table->entries = kzalloc(size, GFP_KERNEL);
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if (!radeon_table->entries)
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return -ENOMEM;
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for (i = 0; i < atom_table->ucNumEntries; i++) {
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radeon_table->entries[i].clk = le16_to_cpu(atom_table->entries[i].usClockLow) |
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(atom_table->entries[i].ucClockHigh << 16);
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radeon_table->entries[i].v = le16_to_cpu(atom_table->entries[i].usVoltage);
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}
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radeon_table->count = atom_table->ucNumEntries;
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return 0;
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}
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int r600_parse_extended_power_table(struct radeon_device *rdev)
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{
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struct radeon_mode_info *mode_info = &rdev->mode_info;
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union power_info *power_info;
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union fan_info *fan_info;
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ATOM_PPLIB_Clock_Voltage_Dependency_Table *dep_table;
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int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
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u16 data_offset;
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u8 frev, crev;
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int ret, i;
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if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
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&frev, &crev, &data_offset))
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return -EINVAL;
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power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
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/* fan table */
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if (power_info->pplib.usTableSize >= sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) {
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if (power_info->pplib3.usFanTableOffset) {
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fan_info = (union fan_info *)(mode_info->atom_context->bios + data_offset +
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le16_to_cpu(power_info->pplib3.usFanTableOffset));
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rdev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst;
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rdev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin);
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rdev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed);
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rdev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh);
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rdev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin);
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rdev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed);
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rdev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh);
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if (fan_info->fan.ucFanTableFormat >= 2)
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rdev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax);
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else
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rdev->pm.dpm.fan.t_max = 10900;
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rdev->pm.dpm.fan.cycle_delay = 100000;
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rdev->pm.dpm.fan.ucode_fan_control = true;
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}
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}
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/* clock dependancy tables */
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if (power_info->pplib.usTableSize >= sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE4)) {
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if (power_info->pplib4.usVddcDependencyOnSCLKOffset) {
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dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
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(mode_info->atom_context->bios + data_offset +
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le16_to_cpu(power_info->pplib4.usVddcDependencyOnSCLKOffset));
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ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
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dep_table);
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if (ret)
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return ret;
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}
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if (power_info->pplib4.usVddciDependencyOnMCLKOffset) {
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dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
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(mode_info->atom_context->bios + data_offset +
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le16_to_cpu(power_info->pplib4.usVddciDependencyOnMCLKOffset));
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ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
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dep_table);
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if (ret) {
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kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
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return ret;
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}
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}
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if (power_info->pplib4.usVddcDependencyOnMCLKOffset) {
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dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
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(mode_info->atom_context->bios + data_offset +
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le16_to_cpu(power_info->pplib4.usVddcDependencyOnMCLKOffset));
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ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
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dep_table);
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if (ret) {
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kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
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kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
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return ret;
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}
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}
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if (power_info->pplib4.usMaxClockVoltageOnDCOffset) {
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ATOM_PPLIB_Clock_Voltage_Limit_Table *clk_v =
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(ATOM_PPLIB_Clock_Voltage_Limit_Table *)
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(mode_info->atom_context->bios + data_offset +
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le16_to_cpu(power_info->pplib4.usMaxClockVoltageOnDCOffset));
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if (clk_v->ucNumEntries) {
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rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk =
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le16_to_cpu(clk_v->entries[0].usSclkLow) |
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(clk_v->entries[0].ucSclkHigh << 16);
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rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk =
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le16_to_cpu(clk_v->entries[0].usMclkLow) |
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(clk_v->entries[0].ucMclkHigh << 16);
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rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc =
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le16_to_cpu(clk_v->entries[0].usVddc);
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rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci =
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le16_to_cpu(clk_v->entries[0].usVddci);
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}
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}
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}
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/* cac data */
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if (power_info->pplib.usTableSize >= sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE5)) {
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rdev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit);
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rdev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit);
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rdev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit);
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if (rdev->pm.dpm.tdp_od_limit)
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rdev->pm.dpm.power_control = true;
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else
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rdev->pm.dpm.power_control = false;
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rdev->pm.dpm.tdp_adjustment = 0;
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rdev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold);
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rdev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage);
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rdev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope);
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if (power_info->pplib5.usCACLeakageTableOffset) {
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ATOM_PPLIB_CAC_Leakage_Table *cac_table =
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(ATOM_PPLIB_CAC_Leakage_Table *)
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(mode_info->atom_context->bios + data_offset +
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le16_to_cpu(power_info->pplib5.usCACLeakageTableOffset));
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u32 size = cac_table->ucNumEntries * sizeof(struct radeon_cac_leakage_table);
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rdev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL);
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if (!rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
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kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
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kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
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kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
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return -ENOMEM;
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}
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for (i = 0; i < cac_table->ucNumEntries; i++) {
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rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc =
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le16_to_cpu(cac_table->entries[i].usVddc);
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rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage =
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le32_to_cpu(cac_table->entries[i].ulLeakageValue);
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}
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rdev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries;
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}
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}
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return 0;
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}
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void r600_free_extended_power_table(struct radeon_device *rdev)
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{
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if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries)
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kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
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if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries)
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kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
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if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries)
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kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
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if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries)
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kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries);
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}
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@ -215,4 +215,7 @@ int r600_set_thermal_temperature_range(struct radeon_device *rdev,
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int min_temp, int max_temp);
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bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor);
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int r600_parse_extended_power_table(struct radeon_device *rdev);
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void r600_free_extended_power_table(struct radeon_device *rdev);
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#endif
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@ -1217,6 +1217,66 @@ struct radeon_dpm_thermal {
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bool high_to_low;
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};
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struct radeon_clock_and_voltage_limits {
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u32 sclk;
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u32 mclk;
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u32 vddc;
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u32 vddci;
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};
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struct radeon_clock_array {
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u32 count;
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u32 *values;
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};
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struct radeon_clock_voltage_dependency_entry {
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u32 clk;
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u16 v;
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};
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struct radeon_clock_voltage_dependency_table {
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u32 count;
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struct radeon_clock_voltage_dependency_entry *entries;
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};
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struct radeon_cac_leakage_entry {
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u16 vddc;
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u32 leakage;
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};
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struct radeon_cac_leakage_table {
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u32 count;
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struct radeon_cac_leakage_entry *entries;
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};
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struct radeon_dpm_dynamic_state {
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struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
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struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
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struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
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struct radeon_clock_array valid_sclk_values;
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struct radeon_clock_array valid_mclk_values;
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struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
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struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
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u32 mclk_sclk_ratio;
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u32 sclk_mclk_delta;
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u16 vddc_vddci_delta;
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u16 min_vddc_for_pcie_gen2;
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struct radeon_cac_leakage_table cac_leakage_table;
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};
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struct radeon_dpm_fan {
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u16 t_min;
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u16 t_med;
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u16 t_high;
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u16 pwm_min;
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u16 pwm_med;
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u16 pwm_high;
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u8 t_hyst;
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u32 cycle_delay;
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u16 t_max;
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bool ucode_fan_control;
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};
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struct radeon_dpm {
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struct radeon_ps *ps;
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/* number of valid power states */
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@ -1239,6 +1299,16 @@ struct radeon_dpm {
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int new_active_crtc_count;
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u32 current_active_crtcs;
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int current_active_crtc_count;
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struct radeon_dpm_dynamic_state dyn_state;
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struct radeon_dpm_fan fan;
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u32 tdp_limit;
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u32 near_tdp_limit;
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u32 sq_ramping_threshold;
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u32 cac_leakage;
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u16 tdp_od_limit;
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u32 tdp_adjustment;
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u16 load_line_slope;
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bool power_control;
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/* special states active */
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bool thermal_active;
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bool uvd_active;
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