mirror of https://gitee.com/openkylin/linux.git
ARM: DRA7: hwmod: Add data for AES IP
DRA7 SoC contains AES crypto hardware accelerator. Add hwmod data for this IP so that it can be utilized by crypto frameworks. Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [t-kristo@ti.com: squash in support for both AES1 and AES2 cores] Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -690,6 +690,50 @@ static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
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.parent_hwmod = &dra7xx_dss_hwmod,
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};
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/* AES (the 'P' (public) device) */
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static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
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.rev_offs = 0x0080,
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.sysc_offs = 0x0084,
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.syss_offs = 0x0088,
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.sysc_flags = SYSS_HAS_RESET_STATUS,
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};
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static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
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.name = "aes",
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.sysc = &dra7xx_aes_sysc,
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.rev = 2,
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};
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/* AES1 */
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static struct omap_hwmod dra7xx_aes1_hwmod = {
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.name = "aes1",
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.class = &dra7xx_aes_hwmod_class,
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.clkdm_name = "l4sec_clkdm",
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.main_clk = "l3_iclk_div",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/* AES2 */
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static struct omap_hwmod dra7xx_aes2_hwmod = {
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.name = "aes2",
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.class = &dra7xx_aes_hwmod_class,
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.clkdm_name = "l4sec_clkdm",
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.main_clk = "l3_iclk_div",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/*
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* 'elm' class
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*
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@ -2957,6 +3001,22 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l3_main_1 -> aes1 */
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static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
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.master = &dra7xx_l3_main_1_hwmod,
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.slave = &dra7xx_aes1_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l3_main_1 -> aes2 */
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static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
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.master = &dra7xx_l3_main_1_hwmod,
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.slave = &dra7xx_aes2_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per2 -> mcasp1 */
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static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
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.master = &dra7xx_l4_per2_hwmod,
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@ -3836,6 +3896,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
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&dra7xx_l3_main_1__dss,
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&dra7xx_l3_main_1__dispc,
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&dra7xx_l3_main_1__hdmi,
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&dra7xx_l3_main_1__aes1,
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&dra7xx_l3_main_1__aes2,
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&dra7xx_l4_per1__elm,
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&dra7xx_l4_wkup__gpio1,
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&dra7xx_l4_per1__gpio2,
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