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Samsung DTS ARM64 changes for v5.2 

1. Use proper clock rates for GSCALER module on TM2 boards.
 2. Add clocks for local paths on DECON and GSCALER modules of
    Exynos5433.
 3. Add Slim SecuritySubSystem to Exynos5433.
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Merge tag 'samsung-dt64-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

Samsung DTS ARM64 changes for v5.2

1. Use proper clock rates for GSCALER module on TM2 boards.
2. Add clocks for local paths on DECON and GSCALER modules of
   Exynos5433.
3. Add Slim SecuritySubSystem to Exynos5433.

* tag 'samsung-dt64-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos: Add SlimSSS to Exynos5433
  arm64: dts: exynos: add DSD/GSD clocks to DECONs and GSCALERs of Exynos5433
  arm64: dts: exynos: configure GSCALER related clocks on TM2

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-04-28 12:29:48 -07:00
parent 1fbdc24775 77fc46976e
commit 629d716187
3 changed files with 34 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
View File

@ -289,6 +289,12 @@ &cmu_mfc {
assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
};
&cmu_mif {
assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
assigned-clock-rates = <0>, <333000000>;
};
&cmu_mscl {
assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
<&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,

6
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
View File

@ -33,7 +33,8 @@ &cmu_disp {
<&cmu_disp CLK_MOUT_DISP_PLL>,
<&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>,
<&cmu_disp CLK_MOUT_SCLK_DSD_USER>;
assigned-clock-parents = <0>, <0>,
<&cmu_mif CLK_ACLK_DISP_333>,
<&cmu_mif CLK_SCLK_DSIM0_DISP>,
@ -45,7 +46,8 @@ &cmu_disp {
<&cmu_disp CLK_FOUT_DISP_PLL>,
<&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
<&cmu_mif CLK_SCLK_DSD_DISP>;
assigned-clock-rates = <250000000>, <400000000>;
};

34
arch/arm64/boot/dts/exynos/exynos5433.dtsi
View File

@ -559,6 +559,15 @@ cmu_imem: clock-controller@11060000 {
<&cmu_top CLK_DIV_ACLK_IMEM_200>;
};
slim_sss: slim-sss@11140000 {
compatible = "samsung,exynos5433-slim-sss";
reg = <0x11140000 0x1000>;
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "aclk", "pclk";
clocks = <&cmu_imem CLK_ACLK_SLIMSSS>,
<&cmu_imem CLK_PCLK_SLIMSSS>;
};
pd_gscl: power-domain@105c4000 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c4000 0x20>;
@ -848,12 +857,13 @@ decon: decon@13800000 {
<&cmu_disp CLK_ACLK_XIU_DECON1X>,
<&cmu_disp CLK_PCLK_SMMU_DECON1X>,
<&cmu_disp CLK_SCLK_DECON_VCLK>,
<&cmu_disp CLK_SCLK_DECON_ECLK>;
<&cmu_disp CLK_SCLK_DECON_ECLK>,
<&cmu_disp CLK_SCLK_DSD>;
clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
"aclk_xiu_decon0x", "pclk_smmu_decon0x",
"aclk_smmu_decon1x", "aclk_xiu_decon1x",
"pclk_smmu_decon1x", "sclk_decon_vclk",
"sclk_decon_eclk";
"sclk_decon_eclk", "dsd";
power-domains = <&pd_disp>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
@ -890,12 +900,13 @@ decon_tv: decon@13880000 {
<&cmu_disp CLK_ACLK_XIU_TV1X>,
<&cmu_disp CLK_PCLK_SMMU_TV1X>,
<&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
<&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
<&cmu_disp CLK_SCLK_DECON_TV_ECLK>,
<&cmu_disp CLK_SCLK_DSD>;
clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
"aclk_xiu_decon0x", "pclk_smmu_decon0x",
"aclk_smmu_decon1x", "aclk_xiu_decon1x",
"pclk_smmu_decon1x", "sclk_decon_vclk",
"sclk_decon_eclk";
"sclk_decon_eclk", "dsd";
samsung,disp-sysreg = <&syscon_disp>;
power-domains = <&pd_disp>;
interrupt-names = "fifo", "vsync", "lcd_sys";
@ -1022,11 +1033,12 @@ gsc_0: video-scaler@13c00000 {
reg = <0x13c00000 0x1000>;
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk", "aclk_xiu",
"aclk_gsclbend";
"aclk_gsclbend", "gsd";
clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
<&cmu_gscl CLK_ACLK_GSCL0>,
<&cmu_gscl CLK_ACLK_XIU_GSCLX>,
<&cmu_gscl CLK_ACLK_GSCLBEND_333>;
<&cmu_gscl CLK_ACLK_GSCLBEND_333>,
<&cmu_gscl CLK_ACLK_GSD>;
iommus = <&sysmmu_gscl0>;
power-domains = <&pd_gscl>;
};
@ -1036,11 +1048,12 @@ gsc_1: video-scaler@13c10000 {
reg = <0x13c10000 0x1000>;
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk", "aclk_xiu",
"aclk_gsclbend";
"aclk_gsclbend", "gsd";
clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
<&cmu_gscl CLK_ACLK_GSCL1>,
<&cmu_gscl CLK_ACLK_XIU_GSCLX>,
<&cmu_gscl CLK_ACLK_GSCLBEND_333>;
<&cmu_gscl CLK_ACLK_GSCLBEND_333>,
<&cmu_gscl CLK_ACLK_GSD>;
iommus = <&sysmmu_gscl1>;
power-domains = <&pd_gscl>;
};
@ -1050,11 +1063,12 @@ gsc_2: video-scaler@13c20000 {
reg = <0x13c20000 0x1000>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk", "aclk_xiu",
"aclk_gsclbend";
"aclk_gsclbend", "gsd";
clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
<&cmu_gscl CLK_ACLK_GSCL2>,
<&cmu_gscl CLK_ACLK_XIU_GSCLX>,
<&cmu_gscl CLK_ACLK_GSCLBEND_333>;
<&cmu_gscl CLK_ACLK_GSCLBEND_333>,
<&cmu_gscl CLK_ACLK_GSD>;
iommus = <&sysmmu_gscl2>;
power-domains = <&pd_gscl>;
};