mirror of https://gitee.com/openkylin/linux.git
mtd: nand: omap: cleanup: replace local references with generic framework names
This patch updates following in omap_nand_probe() and omap_nand_remove() - replaces "info->nand" with "nand_chip" (struct nand_chip *nand_chip) - replaces "info->mtd" with "mtd" (struct mtd_info *mtd) - white-space and formatting cleanup Signed-off-by: Pekon Gupta <pekon@ti.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
Pekon Gupta
Brian Norris
parent
c66d039197
commit
633deb58e1
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@ -1824,10 +1824,12 @@ static int omap_nand_probe(struct platform_device *pdev)
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{
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struct omap_nand_info *info;
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struct omap_nand_platform_data *pdata;
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struct mtd_info *mtd;
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struct nand_chip *nand_chip;
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int err;
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int i, offset;
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dma_cap_mask_t mask;
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unsigned sig;
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dma_cap_mask_t mask;
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unsigned sig;
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struct resource *res;
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struct mtd_part_parser_data ppdata = {};
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@ -1846,17 +1848,16 @@ static int omap_nand_probe(struct platform_device *pdev)
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spin_lock_init(&info->controller.lock);
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init_waitqueue_head(&info->controller.wq);
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info->pdev = pdev;
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info->pdev = pdev;
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info->gpmc_cs = pdata->cs;
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info->reg = pdata->reg;
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info->mtd.priv = &info->nand;
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info->mtd.name = dev_name(&pdev->dev);
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info->mtd.owner = THIS_MODULE;
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info->nand.options = pdata->devsize;
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info->nand.options |= NAND_SKIP_BBTSCAN;
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mtd = &info->mtd;
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mtd->priv = &info->nand;
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mtd->name = dev_name(&pdev->dev);
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mtd->owner = THIS_MODULE;
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nand_chip = &info->nand;
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nand_chip->options = pdata->devsize;
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nand_chip->options |= NAND_SKIP_BBTSCAN;
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#ifdef CONFIG_MTD_NAND_OMAP_BCH
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info->of_node = pdata->of_node;
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#endif
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@ -1877,16 +1878,16 @@ static int omap_nand_probe(struct platform_device *pdev)
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goto out_free_info;
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}
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info->nand.IO_ADDR_R = ioremap(info->phys_base, info->mem_size);
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if (!info->nand.IO_ADDR_R) {
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nand_chip->IO_ADDR_R = ioremap(info->phys_base, info->mem_size);
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if (!nand_chip->IO_ADDR_R) {
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err = -ENOMEM;
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goto out_release_mem_region;
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}
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info->nand.controller = &info->controller;
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nand_chip->controller = &info->controller;
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info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
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info->nand.cmd_ctrl = omap_hwcontrol;
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nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
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nand_chip->cmd_ctrl = omap_hwcontrol;
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/*
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* If RDY/BSY line is connected to OMAP then use the omap ready
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@ -1896,26 +1897,26 @@ static int omap_nand_probe(struct platform_device *pdev)
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* device and read status register until you get a failure or success
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*/
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if (pdata->dev_ready) {
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info->nand.dev_ready = omap_dev_ready;
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info->nand.chip_delay = 0;
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nand_chip->dev_ready = omap_dev_ready;
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nand_chip->chip_delay = 0;
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} else {
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info->nand.waitfunc = omap_wait;
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info->nand.chip_delay = 50;
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nand_chip->waitfunc = omap_wait;
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nand_chip->chip_delay = 50;
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}
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switch (pdata->xfer_type) {
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case NAND_OMAP_PREFETCH_POLLED:
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info->nand.read_buf = omap_read_buf_pref;
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info->nand.write_buf = omap_write_buf_pref;
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nand_chip->read_buf = omap_read_buf_pref;
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nand_chip->write_buf = omap_write_buf_pref;
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break;
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case NAND_OMAP_POLLED:
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if (info->nand.options & NAND_BUSWIDTH_16) {
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info->nand.read_buf = omap_read_buf16;
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info->nand.write_buf = omap_write_buf16;
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if (nand_chip->options & NAND_BUSWIDTH_16) {
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nand_chip->read_buf = omap_read_buf16;
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nand_chip->write_buf = omap_write_buf16;
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} else {
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info->nand.read_buf = omap_read_buf8;
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info->nand.write_buf = omap_write_buf8;
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nand_chip->read_buf = omap_read_buf8;
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nand_chip->write_buf = omap_write_buf8;
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}
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break;
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@ -1944,8 +1945,8 @@ static int omap_nand_probe(struct platform_device *pdev)
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err);
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goto out_release_mem_region;
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}
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info->nand.read_buf = omap_read_buf_dma_pref;
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info->nand.write_buf = omap_write_buf_dma_pref;
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nand_chip->read_buf = omap_read_buf_dma_pref;
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nand_chip->write_buf = omap_write_buf_dma_pref;
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}
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break;
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@ -1980,8 +1981,8 @@ static int omap_nand_probe(struct platform_device *pdev)
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goto out_release_mem_region;
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}
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info->nand.read_buf = omap_read_buf_irq_pref;
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info->nand.write_buf = omap_write_buf_irq_pref;
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nand_chip->read_buf = omap_read_buf_irq_pref;
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nand_chip->write_buf = omap_write_buf_irq_pref;
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break;
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@ -1994,16 +1995,16 @@ static int omap_nand_probe(struct platform_device *pdev)
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/* select the ecc type */
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if (pdata->ecc_opt == OMAP_ECC_HAM1_CODE_HW) {
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info->nand.ecc.bytes = 3;
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info->nand.ecc.size = 512;
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info->nand.ecc.strength = 1;
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info->nand.ecc.calculate = omap_calculate_ecc;
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info->nand.ecc.hwctl = omap_enable_hwecc;
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info->nand.ecc.correct = omap_correct_data;
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info->nand.ecc.mode = NAND_ECC_HW;
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nand_chip->ecc.bytes = 3;
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nand_chip->ecc.size = 512;
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nand_chip->ecc.strength = 1;
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nand_chip->ecc.calculate = omap_calculate_ecc;
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nand_chip->ecc.hwctl = omap_enable_hwecc;
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nand_chip->ecc.correct = omap_correct_data;
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nand_chip->ecc.mode = NAND_ECC_HW;
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} else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
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(pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
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err = omap3_init_bch(&info->mtd, pdata->ecc_opt);
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err = omap3_init_bch(mtd, pdata->ecc_opt);
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if (err) {
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err = -EINVAL;
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goto out_release_mem_region;
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@ -2013,9 +2014,9 @@ static int omap_nand_probe(struct platform_device *pdev)
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/* DIP switches on some boards change between 8 and 16 bit
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* bus widths for flash. Try the other width if the first try fails.
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*/
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if (nand_scan_ident(&info->mtd, 1, NULL)) {
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info->nand.options ^= NAND_BUSWIDTH_16;
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if (nand_scan_ident(&info->mtd, 1, NULL)) {
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if (nand_scan_ident(mtd, 1, NULL)) {
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nand_chip->options ^= NAND_BUSWIDTH_16;
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if (nand_scan_ident(mtd, 1, NULL)) {
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err = -ENXIO;
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goto out_release_mem_region;
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}
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@ -2024,25 +2025,25 @@ static int omap_nand_probe(struct platform_device *pdev)
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/* rom code layout */
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if (pdata->ecc_opt == OMAP_ECC_HAM1_CODE_HW) {
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if (info->nand.options & NAND_BUSWIDTH_16)
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if (nand_chip->options & NAND_BUSWIDTH_16) {
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offset = 2;
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else {
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} else {
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offset = 1;
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info->nand.badblock_pattern = &bb_descrip_flashbased;
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nand_chip->badblock_pattern = &bb_descrip_flashbased;
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}
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omap_oobinfo.eccbytes = 3 * (info->mtd.writesize / 512);
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omap_oobinfo.eccbytes = 3 * (mtd->writesize / 512);
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for (i = 0; i < omap_oobinfo.eccbytes; i++)
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omap_oobinfo.eccpos[i] = i+offset;
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omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
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omap_oobinfo.oobfree->length = info->mtd.oobsize -
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omap_oobinfo.oobfree->length = mtd->oobsize -
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(offset + omap_oobinfo.eccbytes);
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info->nand.ecc.layout = &omap_oobinfo;
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nand_chip->ecc.layout = &omap_oobinfo;
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} else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
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(pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
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/* build OOB layout for BCH ECC correction */
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err = omap3_init_bch_tail(&info->mtd);
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err = omap3_init_bch_tail(mtd);
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if (err) {
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err = -EINVAL;
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goto out_release_mem_region;
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@ -2050,16 +2051,16 @@ static int omap_nand_probe(struct platform_device *pdev)
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}
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/* second phase scan */
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if (nand_scan_tail(&info->mtd)) {
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if (nand_scan_tail(mtd)) {
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err = -ENXIO;
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goto out_release_mem_region;
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}
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ppdata.of_node = pdata->of_node;
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mtd_device_parse_register(&info->mtd, NULL, &ppdata, pdata->parts,
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mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts,
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pdata->nr_parts);
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platform_set_drvdata(pdev, &info->mtd);
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platform_set_drvdata(pdev, mtd);
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return 0;
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@ -2080,9 +2081,10 @@ static int omap_nand_probe(struct platform_device *pdev)
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static int omap_nand_remove(struct platform_device *pdev)
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{
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struct mtd_info *mtd = platform_get_drvdata(pdev);
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struct nand_chip *nand_chip = mtd->priv;
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struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
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mtd);
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omap3_free_bch(&info->mtd);
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omap3_free_bch(mtd);
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if (info->dma)
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dma_release_channel(info->dma);
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@ -2093,8 +2095,8 @@ static int omap_nand_remove(struct platform_device *pdev)
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free_irq(info->gpmc_irq_fifo, info);
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/* Release NAND device, its internal structures and partitions */
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nand_release(&info->mtd);
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iounmap(info->nand.IO_ADDR_R);
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nand_release(mtd);
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iounmap(nand_chip->IO_ADDR_R);
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release_mem_region(info->phys_base, info->mem_size);
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kfree(info);
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return 0;
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