mirror of https://gitee.com/openkylin/linux.git
mmc: mediatek: add HS400 support
add HS400 mode and tune support Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Chaotian Jing
Ulf Hansson
parent
9979dbe515
commit
6397b7f5f4
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@ -26,6 +26,7 @@
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/mmc/card.h>
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@ -72,6 +73,8 @@
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#define MSDC_PATCH_BIT 0xb0
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#define MSDC_PATCH_BIT1 0xb4
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#define MSDC_PAD_TUNE 0xec
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#define PAD_DS_TUNE 0x188
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#define EMMC50_CFG0 0x208
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/*--------------------------------------------------------------------------*/
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/* Register Mask */
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@ -88,6 +91,7 @@
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#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
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#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
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#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
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#define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
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/* MSDC_IOCON mask */
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#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
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@ -205,6 +209,17 @@
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#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
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#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
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#define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
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#define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
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#define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
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#define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
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#define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
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#define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
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#define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
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#define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
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#define REQ_CMD_EIO (0x1 << 0)
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#define REQ_CMD_TMO (0x1 << 1)
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#define REQ_DAT_ERR (0x1 << 2)
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@ -220,6 +235,7 @@
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#define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
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#define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
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#define PAD_DELAY_MAX 32 /* PAD delay cells */
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/*--------------------------------------------------------------------------*/
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/* Descriptor Structure */
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/*--------------------------------------------------------------------------*/
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@ -266,6 +282,14 @@ struct msdc_save_para {
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u32 pad_tune;
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u32 patch_bit0;
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u32 patch_bit1;
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u32 pad_ds_tune;
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u32 emmc50_cfg0;
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};
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struct msdc_delay_phase {
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u8 maxlen;
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u8 start;
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u8 final_phase;
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};
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struct msdc_host {
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@ -300,6 +324,7 @@ struct msdc_host {
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u32 sclk; /* SD/MS bus clock frequency */
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unsigned char timing;
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bool vqmmc_enabled;
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u32 hs400_ds_delay;
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struct msdc_save_para save_para; /* used when gate HCLK */
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};
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@ -505,9 +530,15 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
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flags = readl(host->base + MSDC_INTEN);
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sdr_clr_bits(host->base + MSDC_INTEN, flags);
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sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
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if (timing == MMC_TIMING_UHS_DDR50 ||
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timing == MMC_TIMING_MMC_DDR52) {
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mode = 0x2; /* ddr mode and use divisor */
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timing == MMC_TIMING_MMC_DDR52 ||
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timing == MMC_TIMING_MMC_HS400) {
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if (timing == MMC_TIMING_MMC_HS400)
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mode = 0x3;
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else
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mode = 0x2; /* ddr mode and use divisor */
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if (hz >= (host->src_clk_freq >> 2)) {
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div = 0; /* mean div = 1/4 */
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sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
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@ -516,6 +547,14 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
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sclk = (host->src_clk_freq >> 2) / div;
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div = (div >> 1);
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}
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if (timing == MMC_TIMING_MMC_HS400 &&
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hz >= (host->src_clk_freq >> 1)) {
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sdr_set_bits(host->base + MSDC_CFG,
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MSDC_CFG_HS400_CK_MODE);
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sclk = host->src_clk_freq >> 1;
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div = 0; /* div is ignore when bit18 is set */
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}
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} else if (hz >= host->src_clk_freq) {
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mode = 0x1; /* no divisor */
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div = 0;
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@ -894,7 +933,7 @@ static void msdc_data_xfer_next(struct msdc_host *host,
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struct mmc_request *mrq, struct mmc_data *data)
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{
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if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
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(!data->bytes_xfered || !mrq->sbc))
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!mrq->sbc)
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msdc_start_command(host, mrq, mrq->stop);
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else
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msdc_request_done(host, mrq);
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@ -940,6 +979,8 @@ static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
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if (events & MSDC_INT_DATTMO)
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data->error = -ETIMEDOUT;
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else if (events & MSDC_INT_DATCRCERR)
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data->error = -EILSEQ;
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dev_err(host->dev, "%s: cmd=%d; blocks=%d",
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__func__, mrq->cmd->opcode, data->blocks);
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@ -1111,10 +1152,12 @@ static void msdc_init_hw(struct msdc_host *host)
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writel(0, host->base + MSDC_PAD_TUNE);
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writel(0, host->base + MSDC_IOCON);
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sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
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writel(0x403c004f, host->base + MSDC_PATCH_BIT);
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sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
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writel(0x403c0046, host->base + MSDC_PATCH_BIT);
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sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
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writel(0xffff0089, host->base + MSDC_PATCH_BIT1);
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sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
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/* Configure to enable SDIO mode.
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* it's must otherwise sdio cmd5 failed
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*/
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@ -1172,6 +1215,7 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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switch (ios->power_mode) {
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case MMC_POWER_UP:
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if (!IS_ERR(mmc->supply.vmmc)) {
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msdc_init_hw(host);
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ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
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ios->vdd);
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if (ret) {
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@ -1210,6 +1254,190 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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pm_runtime_put_autosuspend(host->dev);
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}
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static u32 test_delay_bit(u32 delay, u32 bit)
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{
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bit %= PAD_DELAY_MAX;
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return delay & (1 << bit);
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}
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static int get_delay_len(u32 delay, u32 start_bit)
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{
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int i;
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for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
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if (test_delay_bit(delay, start_bit + i) == 0)
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return i;
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}
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return PAD_DELAY_MAX - start_bit;
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}
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static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
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{
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int start = 0, len = 0;
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int start_final = 0, len_final = 0;
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u8 final_phase = 0xff;
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struct msdc_delay_phase delay_phase;
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if (delay == 0) {
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dev_err(host->dev, "phase error: [map:%x]\n", delay);
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delay_phase.final_phase = final_phase;
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return delay_phase;
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}
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while (start < PAD_DELAY_MAX) {
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len = get_delay_len(delay, start);
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if (len_final < len) {
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start_final = start;
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len_final = len;
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}
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start += len ? len : 1;
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if (len >= 8 && start_final < 4)
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break;
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}
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/* The rule is that to find the smallest delay cell */
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if (start_final == 0)
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final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
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else
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final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
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dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
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delay, len_final, final_phase);
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delay_phase.maxlen = len_final;
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delay_phase.start = start_final;
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delay_phase.final_phase = final_phase;
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return delay_phase;
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}
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static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
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{
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struct msdc_host *host = mmc_priv(mmc);
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u32 rise_delay = 0, fall_delay = 0;
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struct msdc_delay_phase final_rise_delay, final_fall_delay;
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u8 final_delay, final_maxlen;
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int cmd_err;
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int i;
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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for (i = 0 ; i < PAD_DELAY_MAX; i++) {
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sdr_set_field(host->base + MSDC_PAD_TUNE,
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MSDC_PAD_TUNE_CMDRDLY, i);
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mmc_send_tuning(mmc, opcode, &cmd_err);
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if (!cmd_err)
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rise_delay |= (1 << i);
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}
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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sdr_set_field(host->base + MSDC_PAD_TUNE,
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MSDC_PAD_TUNE_CMDRDLY, i);
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mmc_send_tuning(mmc, opcode, &cmd_err);
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if (!cmd_err)
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fall_delay |= (1 << i);
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}
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final_rise_delay = get_best_delay(host, rise_delay);
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final_fall_delay = get_best_delay(host, fall_delay);
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final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
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if (final_maxlen == final_rise_delay.maxlen) {
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
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final_rise_delay.final_phase);
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final_delay = final_rise_delay.final_phase;
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} else {
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
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final_fall_delay.final_phase);
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final_delay = final_fall_delay.final_phase;
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}
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return final_delay == 0xff ? -EIO : 0;
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}
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static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
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{
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struct msdc_host *host = mmc_priv(mmc);
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u32 rise_delay = 0, fall_delay = 0;
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struct msdc_delay_phase final_rise_delay, final_fall_delay;
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u8 final_delay, final_maxlen;
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int i, ret;
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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for (i = 0 ; i < PAD_DELAY_MAX; i++) {
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sdr_set_field(host->base + MSDC_PAD_TUNE,
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MSDC_PAD_TUNE_DATRRDLY, i);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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rise_delay |= (1 << i);
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}
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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sdr_set_field(host->base + MSDC_PAD_TUNE,
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MSDC_PAD_TUNE_DATRRDLY, i);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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fall_delay |= (1 << i);
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}
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final_rise_delay = get_best_delay(host, rise_delay);
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final_fall_delay = get_best_delay(host, fall_delay);
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final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
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/* Rising edge is more stable, prefer to use it */
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if (final_rise_delay.maxlen >= 10)
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final_maxlen = final_rise_delay.maxlen;
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if (final_maxlen == final_rise_delay.maxlen) {
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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sdr_set_field(host->base + MSDC_PAD_TUNE,
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MSDC_PAD_TUNE_DATRRDLY,
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final_rise_delay.final_phase);
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final_delay = final_rise_delay.final_phase;
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} else {
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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sdr_set_field(host->base + MSDC_PAD_TUNE,
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MSDC_PAD_TUNE_DATRRDLY,
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final_fall_delay.final_phase);
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final_delay = final_fall_delay.final_phase;
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}
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return final_delay == 0xff ? -EIO : 0;
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}
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static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
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{
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struct msdc_host *host = mmc_priv(mmc);
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int ret;
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pm_runtime_get_sync(host->dev);
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ret = msdc_tune_response(mmc, opcode);
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if (ret == -EIO) {
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dev_err(host->dev, "Tune response fail!\n");
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goto out;
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}
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ret = msdc_tune_data(mmc, opcode);
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if (ret == -EIO)
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dev_err(host->dev, "Tune data fail!\n");
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out:
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pm_runtime_mark_last_busy(host->dev);
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pm_runtime_put_autosuspend(host->dev);
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return ret;
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}
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static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct msdc_host *host = mmc_priv(mmc);
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writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
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return 0;
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}
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static void msdc_hw_reset(struct mmc_host *mmc)
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{
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struct msdc_host *host = mmc_priv(mmc);
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@ -1226,6 +1454,8 @@ static struct mmc_host_ops mt_msdc_ops = {
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.set_ios = msdc_ops_set_ios,
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.start_signal_voltage_switch = msdc_ops_switch_volt,
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.card_busy = msdc_card_busy,
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.execute_tuning = msdc_execute_tuning,
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.prepare_hs400_tuning = msdc_prepare_hs400_tuning,
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.hw_reset = msdc_hw_reset,
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};
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@ -1300,6 +1530,11 @@ static int msdc_drv_probe(struct platform_device *pdev)
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goto host_free;
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}
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if (!of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
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&host->hs400_ds_delay))
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dev_dbg(&pdev->dev, "hs400-ds-delay: %x\n",
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host->hs400_ds_delay);
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host->dev = &pdev->dev;
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host->mmc = mmc;
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host->src_clk_freq = clk_get_rate(host->src_clk);
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@ -1410,6 +1645,8 @@ static void msdc_save_reg(struct msdc_host *host)
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host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
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host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
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host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
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host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
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host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
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}
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static void msdc_restore_reg(struct msdc_host *host)
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@ -1420,6 +1657,8 @@ static void msdc_restore_reg(struct msdc_host *host)
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writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE);
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writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
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writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
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writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
|
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writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
|
||||
}
|
||||
|
||||
static int msdc_runtime_suspend(struct device *dev)
|
||||
|
|
|
|||
Loading…
Reference in New Issue