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drm/amd/pp: Move common code to smu_helper.c 

Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-04-08 16:57:55 +08:00 committed by Alex Deucher
parent 8db42a7013
commit 63c2f7ed7b
4 changed files with 109 additions and 70 deletions
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30
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
View File

@ -793,32 +793,6 @@ static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
return 0;
}
static int smu7_get_voltage_dependency_table(
const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table,
struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
{
uint8_t i = 0;
PP_ASSERT_WITH_CODE((0 != allowed_dep_table->count),
"Voltage Lookup Table empty",
return -EINVAL);
dep_table->count = allowed_dep_table->count;
for (i=0; i<dep_table->count; i++) {
dep_table->entries[i].clk = allowed_dep_table->entries[i].clk;
dep_table->entries[i].vddInd = allowed_dep_table->entries[i].vddInd;
dep_table->entries[i].vdd_offset = allowed_dep_table->entries[i].vdd_offset;
dep_table->entries[i].vddc = allowed_dep_table->entries[i].vddc;
dep_table->entries[i].vddgfx = allowed_dep_table->entries[i].vddgfx;
dep_table->entries[i].vddci = allowed_dep_table->entries[i].vddci;
dep_table->entries[i].mvdd = allowed_dep_table->entries[i].mvdd;
dep_table->entries[i].phases = allowed_dep_table->entries[i].phases;
dep_table->entries[i].cks_enable = allowed_dep_table->entries[i].cks_enable;
dep_table->entries[i].cks_voffset = allowed_dep_table->entries[i].cks_voffset;
}
return 0;
}
static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@ -846,7 +820,7 @@ static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
entries[i].vddc = dep_sclk_table->entries[i].vddc;
}
smu7_get_voltage_dependency_table(dep_sclk_table,
smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table,
(struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
odn_table->odn_memory_clock_dpm_levels.num_of_pl =
@ -858,7 +832,7 @@ static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
entries[i].vddc = dep_mclk_table->entries[i].vddc;
}
smu7_get_voltage_dependency_table(dep_mclk_table,
smu_get_voltage_dependency_table_ppt_v1(dep_mclk_table,
(struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
return 0;

82
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
View File

@ -624,3 +624,85 @@ void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size,
return NULL;
}
int smu_get_voltage_dependency_table_ppt_v1(
const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table,
struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
{
uint8_t i = 0;
PP_ASSERT_WITH_CODE((0 != allowed_dep_table->count),
"Voltage Lookup Table empty",
return -EINVAL);
dep_table->count = allowed_dep_table->count;
for (i=0; i<dep_table->count; i++) {
dep_table->entries[i].clk = allowed_dep_table->entries[i].clk;
dep_table->entries[i].vddInd = allowed_dep_table->entries[i].vddInd;
dep_table->entries[i].vdd_offset = allowed_dep_table->entries[i].vdd_offset;
dep_table->entries[i].vddc = allowed_dep_table->entries[i].vddc;
dep_table->entries[i].vddgfx = allowed_dep_table->entries[i].vddgfx;
dep_table->entries[i].vddci = allowed_dep_table->entries[i].vddci;
dep_table->entries[i].mvdd = allowed_dep_table->entries[i].mvdd;
dep_table->entries[i].phases = allowed_dep_table->entries[i].phases;
dep_table->entries[i].cks_enable = allowed_dep_table->entries[i].cks_enable;
dep_table->entries[i].cks_voffset = allowed_dep_table->entries[i].cks_voffset;
}
return 0;
}
int smu_set_watermarks_for_clocks_ranges(void *wt_table,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
{
uint32_t i;
struct watermarks *table = wt_table;
if (!table || wm_with_clock_ranges)
return -EINVAL;
if (wm_with_clock_ranges->num_wm_sets_dmif > 4 || wm_with_clock_ranges->num_wm_sets_mcif > 4)
return -EINVAL;
for (i = 0; i < wm_with_clock_ranges->num_wm_sets_dmif; i++) {
table->WatermarkRow[1][i].MinClock =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_dmif[i].wm_min_dcefclk_in_khz) /
100);
table->WatermarkRow[1][i].MaxClock =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_dmif[i].wm_max_dcefclk_in_khz) /
100);
table->WatermarkRow[1][i].MinUclk =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_dmif[i].wm_min_memclk_in_khz) /
100);
table->WatermarkRow[1][i].MaxUclk =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_dmif[i].wm_max_memclk_in_khz) /
100);
table->WatermarkRow[1][i].WmSetting = (uint8_t)
wm_with_clock_ranges->wm_sets_dmif[i].wm_set_id;
}
for (i = 0; i < wm_with_clock_ranges->num_wm_sets_mcif; i++) {
table->WatermarkRow[0][i].MinClock =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_mcif[i].wm_min_socclk_in_khz) /
100);
table->WatermarkRow[0][i].MaxClock =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_mcif[i].wm_max_socclk_in_khz) /
100);
table->WatermarkRow[0][i].MinUclk =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_mcif[i].wm_min_memclk_in_khz) /
100);
table->WatermarkRow[0][i].MaxUclk =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_mcif[i].wm_max_memclk_in_khz) /
100);
table->WatermarkRow[0][i].WmSetting = (uint8_t)
wm_with_clock_ranges->wm_sets_mcif[i].wm_set_id;
}
return 0;
}

24
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
View File

@ -26,10 +26,27 @@
struct pp_atomctrl_voltage_table;
struct pp_hwmgr;
struct phm_ppt_v1_voltage_lookup_table;
struct Watermarks_t;
struct pp_wm_sets_with_clock_ranges_soc15;
uint8_t convert_to_vid(uint16_t vddc);
uint16_t convert_to_vddc(uint8_t vid);
struct watermark_row_generic_t {
uint16_t MinClock;
uint16_t MaxClock;
uint16_t MinUclk;
uint16_t MaxUclk;
uint8_t WmSetting;
uint8_t Padding[3];
};
struct watermarks {
struct watermark_row_generic_t WatermarkRow[2][4];
uint32_t padding[7];
};
extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
uint32_t index,
uint32_t value, uint32_t mask);
@ -85,6 +102,13 @@ int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr);
void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size,
uint8_t *frev, uint8_t *crev);
int smu_get_voltage_dependency_table_ppt_v1(
const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table,
struct phm_ppt_v1_clock_voltage_dependency_table *dep_table);
int smu_set_watermarks_for_clocks_ranges(void *wt_table,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK

43
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
View File

@ -4367,50 +4367,9 @@ static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
struct vega10_hwmgr *data = hwmgr->backend;
Watermarks_t *table = &(data->smc_state_table.water_marks_table);
int result = 0;
uint32_t i;
if (!data->registry_data.disable_water_mark) {
for (i = 0; i < wm_with_clock_ranges->num_wm_sets_dmif; i++) {
table->WatermarkRow[WM_DCEFCLK][i].MinClock =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_dmif[i].wm_min_dcefclk_in_khz) /
100);
table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_dmif[i].wm_max_dcefclk_in_khz) /
100);
table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_dmif[i].wm_min_memclk_in_khz) /
100);
table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_dmif[i].wm_max_memclk_in_khz) /
100);
table->WatermarkRow[WM_DCEFCLK][i].WmSetting = (uint8_t)
wm_with_clock_ranges->wm_sets_dmif[i].wm_set_id;
}
for (i = 0; i < wm_with_clock_ranges->num_wm_sets_mcif; i++) {
table->WatermarkRow[WM_SOCCLK][i].MinClock =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_mcif[i].wm_min_socclk_in_khz) /
100);
table->WatermarkRow[WM_SOCCLK][i].MaxClock =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_mcif[i].wm_max_socclk_in_khz) /
100);
table->WatermarkRow[WM_SOCCLK][i].MinUclk =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_mcif[i].wm_min_memclk_in_khz) /
100);
table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_sets_mcif[i].wm_max_memclk_in_khz) /
100);
table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
wm_with_clock_ranges->wm_sets_mcif[i].wm_set_id;
}
smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
data->water_marks_bitmap = WaterMarksExist;
}