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drm/i915: Always load the display palette before enabling the pipe 

Loading the palette after the planes are enabled can risk showing
incorrect colors. ILK+ already load the palette before even the pipe
is enabled. Just follow the same order for gen2-4 and VLV.

According to BSpec the requirements for palette access are
display core clock and display PLL running. In certain platforms
just the core clock may be enough. But we definitely should have both
running when this gets called during the modeset.

v2: Amend the commit message with some display PLL/core clock info

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2013-06-04 13:48:59 +03:00 committed by Daniel Vetter
parent 5434fd926d
commit 63cbb07476
1 changed files with 4 additions and 2 deletions
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6
drivers/gpu/drm/i915/intel_display.c
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@ -3618,10 +3618,11 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
/* Enable panel fitting for eDP */
i9xx_pfit_enable(intel_crtc);
intel_crtc_load_lut(crtc);
intel_enable_pipe(dev_priv, pipe, false);
intel_enable_plane(dev_priv, plane, pipe);
intel_crtc_load_lut(crtc);
intel_update_fbc(dev);
/* Give the overlay scaler a chance to enable if it's on this pipe */
@ -3657,12 +3658,13 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
/* Enable panel fitting for LVDS */
i9xx_pfit_enable(intel_crtc);
intel_crtc_load_lut(crtc);
intel_enable_pipe(dev_priv, pipe, false);
intel_enable_plane(dev_priv, plane, pipe);
if (IS_G4X(dev))
g4x_fixup_plane(dev_priv, pipe);
intel_crtc_load_lut(crtc);
intel_update_fbc(dev);
/* Give the overlay scaler a chance to enable if it's on this pipe */