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drm/amdgpu: handle multiple MM nodes in the VMs v2
This allows us to map scattered VRAM BOs to the VMs. v2: fix offset handling, use pfn instead of offset, fix PAGE_SIZE != AMDGPU_GPU_PAGE_SIZE case Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Tested-by: Mike Lothian <mike@fireburn.co.uk> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1065,8 +1065,8 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
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* @pages_addr: DMA addresses to use for mapping
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* @vm: requested vm
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* @mapping: mapped range and flags to use for the update
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* @addr: addr to set the area to
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* @flags: HW flags for the mapping
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* @nodes: array of drm_mm_nodes with the MC addresses
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* @fence: optional resulting fence
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*
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* Split the mapping into smaller chunks so that each update fits
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@ -1079,12 +1079,11 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
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dma_addr_t *pages_addr,
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struct amdgpu_vm *vm,
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struct amdgpu_bo_va_mapping *mapping,
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uint32_t flags, uint64_t addr,
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uint32_t flags,
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struct drm_mm_node *nodes,
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struct fence **fence)
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{
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const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE;
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uint64_t src = 0, start = mapping->it.start;
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uint64_t pfn, src = 0, start = mapping->it.start;
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int r;
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/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
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@ -1097,23 +1096,40 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
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trace_amdgpu_vm_bo_update(mapping);
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if (pages_addr) {
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if (flags == gtt_flags)
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src = adev->gart.table_addr + (addr >> 12) * 8;
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addr = 0;
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pfn = mapping->offset >> PAGE_SHIFT;
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if (nodes) {
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while (pfn >= nodes->size) {
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pfn -= nodes->size;
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++nodes;
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}
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}
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addr += mapping->offset;
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if (!pages_addr || src)
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return amdgpu_vm_bo_update_mapping(adev, exclusive,
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src, pages_addr, vm,
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start, mapping->it.last,
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flags, addr, fence);
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do {
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uint64_t max_entries;
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uint64_t addr, last;
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while (start != mapping->it.last + 1) {
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uint64_t last;
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if (nodes) {
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addr = nodes->start << PAGE_SHIFT;
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max_entries = (nodes->size - pfn) *
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(PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
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} else {
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addr = 0;
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max_entries = S64_MAX;
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}
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last = min((uint64_t)mapping->it.last, start + max_size - 1);
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if (pages_addr) {
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if (flags == gtt_flags)
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src = adev->gart.table_addr +
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(addr >> AMDGPU_GPU_PAGE_SHIFT) * 8;
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else
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max_entries = min(max_entries, 16ull * 1024ull);
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addr = 0;
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} else if (flags & AMDGPU_PTE_VALID) {
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addr += adev->vm_manager.vram_base_offset;
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}
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addr += pfn << PAGE_SHIFT;
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last = min((uint64_t)mapping->it.last, start + max_entries - 1);
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r = amdgpu_vm_bo_update_mapping(adev, exclusive,
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src, pages_addr, vm,
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start, last, flags, addr,
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@ -1121,9 +1137,14 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
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if (r)
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return r;
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pfn += last - start + 1;
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if (nodes && nodes->size == pfn) {
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pfn = 0;
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++nodes;
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}
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start = last + 1;
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addr += max_size * AMDGPU_GPU_PAGE_SIZE;
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}
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} while (unlikely(start != mapping->it.last + 1));
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return 0;
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}
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@ -1147,34 +1168,24 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
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dma_addr_t *pages_addr = NULL;
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uint32_t gtt_flags, flags;
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struct ttm_mem_reg *mem;
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struct drm_mm_node *nodes;
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struct fence *exclusive;
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uint64_t addr;
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int r;
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if (clear) {
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mem = NULL;
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addr = 0;
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nodes = NULL;
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exclusive = NULL;
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} else {
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struct ttm_dma_tt *ttm;
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mem = &bo_va->bo->tbo.mem;
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addr = (u64)mem->start << PAGE_SHIFT;
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switch (mem->mem_type) {
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case TTM_PL_TT:
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nodes = mem->mm_node;
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if (mem->mem_type == TTM_PL_TT) {
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ttm = container_of(bo_va->bo->tbo.ttm, struct
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ttm_dma_tt, ttm);
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pages_addr = ttm->dma_address;
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break;
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case TTM_PL_VRAM:
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addr += adev->vm_manager.vram_base_offset;
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break;
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default:
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break;
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}
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exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv);
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}
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@ -1190,7 +1201,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
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list_for_each_entry(mapping, &bo_va->invalids, list) {
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r = amdgpu_vm_bo_split_mapping(adev, exclusive,
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gtt_flags, pages_addr, vm,
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mapping, flags, addr,
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mapping, flags, nodes,
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&bo_va->last_pt_update);
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if (r)
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return r;
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