mirror of https://gitee.com/openkylin/linux.git
ARM: dts: sun9i: Switch to new clock bindings
Now that we have a full clock driver for sun9i, switch to it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai
Maxime Ripard
parent
783ab76ae5
commit
64507fe38d
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@ -48,6 +48,13 @@
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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#include <dt-bindings/clock/sun9i-a80-ccu.h>
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#include <dt-bindings/clock/sun9i-a80-de.h>
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#include <dt-bindings/clock/sun9i-a80-usb.h>
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#include <dt-bindings/reset/sun9i-a80-ccu.h>
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#include <dt-bindings/reset/sun9i-a80-de.h>
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#include <dt-bindings/reset/sun9i-a80-usb.h>
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/ {
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interrupt-parent = <&gic>;
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@ -159,228 +166,13 @@ osc32k: osc32k_clk {
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clock-output-names = "osc32k";
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};
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usb_mod_clk: clk@00a08000 {
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#clock-cells = <1>;
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#reset-cells = <1>;
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compatible = "allwinner,sun9i-a80-usb-mod-clk";
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reg = <0x00a08000 0x4>;
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clocks = <&ahb1_gates 1>;
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clock-output-names = "usb0_ahb", "usb_ohci0",
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"usb1_ahb", "usb_ohci1",
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"usb2_ahb", "usb_ohci2";
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};
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usb_phy_clk: clk@00a08004 {
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#clock-cells = <1>;
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#reset-cells = <1>;
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compatible = "allwinner,sun9i-a80-usb-phy-clk";
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reg = <0x00a08004 0x4>;
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clocks = <&ahb1_gates 1>;
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clock-output-names = "usb_phy0", "usb_hsic1_480M",
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"usb_phy1", "usb_hsic2_480M",
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"usb_phy2", "usb_hsic_12M";
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};
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pll3: clk@06000008 {
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/* placeholder until implemented */
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-rate = <0>;
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clock-output-names = "pll3";
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};
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pll4: clk@0600000c {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-pll4-clk";
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reg = <0x0600000c 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll4";
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};
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pll12: clk@0600002c {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-pll4-clk";
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reg = <0x0600002c 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll12";
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};
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gt_clk: clk@0600005c {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-gt-clk";
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reg = <0x0600005c 0x4>;
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clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
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clock-output-names = "gt";
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};
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ahb0: clk@06000060 {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-ahb-clk";
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reg = <0x06000060 0x4>;
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clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
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clock-output-names = "ahb0";
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};
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ahb1: clk@06000064 {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-ahb-clk";
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reg = <0x06000064 0x4>;
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clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
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clock-output-names = "ahb1";
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};
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ahb2: clk@06000068 {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-ahb-clk";
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reg = <0x06000068 0x4>;
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clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
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clock-output-names = "ahb2";
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};
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apb0: clk@06000070 {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-apb0-clk";
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reg = <0x06000070 0x4>;
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clocks = <&osc24M>, <&pll4>;
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clock-output-names = "apb0";
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};
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apb1: clk@06000074 {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-apb1-clk";
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reg = <0x06000074 0x4>;
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clocks = <&osc24M>, <&pll4>;
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clock-output-names = "apb1";
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};
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cci400_clk: clk@06000078 {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-gt-clk";
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reg = <0x06000078 0x4>;
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clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
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clock-output-names = "cci400";
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};
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mmc0_clk: clk@06000410 {
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#clock-cells = <1>;
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compatible = "allwinner,sun9i-a80-mmc-clk";
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reg = <0x06000410 0x4>;
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clocks = <&osc24M>, <&pll4>;
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clock-output-names = "mmc0", "mmc0_output",
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"mmc0_sample";
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};
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mmc1_clk: clk@06000414 {
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#clock-cells = <1>;
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compatible = "allwinner,sun9i-a80-mmc-clk";
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reg = <0x06000414 0x4>;
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clocks = <&osc24M>, <&pll4>;
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clock-output-names = "mmc1", "mmc1_output",
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"mmc1_sample";
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};
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mmc2_clk: clk@06000418 {
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#clock-cells = <1>;
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compatible = "allwinner,sun9i-a80-mmc-clk";
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reg = <0x06000418 0x4>;
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clocks = <&osc24M>, <&pll4>;
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clock-output-names = "mmc2", "mmc2_output",
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"mmc2_sample";
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};
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mmc3_clk: clk@0600041c {
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#clock-cells = <1>;
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compatible = "allwinner,sun9i-a80-mmc-clk";
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reg = <0x0600041c 0x4>;
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clocks = <&osc24M>, <&pll4>;
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clock-output-names = "mmc3", "mmc3_output",
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"mmc3_sample";
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};
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ahb0_gates: clk@06000580 {
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#clock-cells = <1>;
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compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
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reg = <0x06000580 0x4>;
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clocks = <&ahb0>;
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clock-indices = <0>, <1>, <3>,
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<5>, <8>, <12>,
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<13>, <14>,
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<15>, <16>, <18>,
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<20>, <21>, <22>,
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<23>;
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clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
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"ahb0_ss", "ahb0_sd", "ahb0_nand1",
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"ahb0_nand0", "ahb0_sdram",
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"ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
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"ahb0_spi0", "ahb0_spi1", "ahb0_spi2",
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"ahb0_spi3";
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};
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ahb1_gates: clk@06000584 {
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#clock-cells = <1>;
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compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
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reg = <0x06000584 0x4>;
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clocks = <&ahb1>;
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clock-indices = <0>, <1>,
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<17>, <21>,
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<22>, <23>,
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<24>;
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clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
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"ahb1_gmac", "ahb1_msgbox",
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"ahb1_spinlock", "ahb1_hstimer",
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"ahb1_dma";
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};
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ahb2_gates: clk@06000588 {
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#clock-cells = <1>;
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compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
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reg = <0x06000588 0x4>;
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clocks = <&ahb2>;
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clock-indices = <0>, <1>,
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<2>, <4>, <5>,
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<7>, <8>, <11>;
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clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
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"ahb2_edp", "ahb2_csi", "ahb2_hdmi",
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"ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
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};
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apb0_gates: clk@06000590 {
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#clock-cells = <1>;
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compatible = "allwinner,sun9i-a80-apb0-gates-clk";
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reg = <0x06000590 0x4>;
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clocks = <&apb0>;
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clock-indices = <1>, <5>,
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<11>, <12>, <13>,
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<15>, <17>, <18>,
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<19>;
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clock-output-names = "apb0_spdif", "apb0_pio",
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"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
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"apb0_lradc", "apb0_gpadc", "apb0_twd",
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"apb0_cirtx";
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};
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apb1_gates: clk@06000594 {
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#clock-cells = <1>;
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compatible = "allwinner,sun9i-a80-apb1-gates-clk";
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reg = <0x06000594 0x4>;
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clocks = <&apb1>;
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clock-indices = <0>, <1>,
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<2>, <3>, <4>,
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<16>, <17>,
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<18>, <19>,
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<20>, <21>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
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"apb1_uart0", "apb1_uart1",
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"apb1_uart2", "apb1_uart3",
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"apb1_uart4", "apb1_uart5";
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};
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cpus_clk: clk@08001410 {
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compatible = "allwinner,sun9i-a80-cpus-clk";
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reg = <0x08001410 0x4>;
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#clock-cells = <0>;
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clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
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clocks = <&osc32k>, <&osc24M>,
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<&ccu CLK_PLL_PERIPH0>,
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<&ccu CLK_PLL_AUDIO>;
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clock-output-names = "cpus";
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};
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@ -453,8 +245,8 @@ ehci0: usb@00a00000 {
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compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
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reg = <0x00a00000 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usb_mod_clk 1>;
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resets = <&usb_mod_clk 17>;
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clocks = <&usb_clocks CLK_BUS_HCI0>;
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resets = <&usb_clocks RST_USB0_HCI>;
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phys = <&usbphy1>;
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phy-names = "usb";
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status = "disabled";
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@ -464,8 +256,9 @@ ohci0: usb@00a00400 {
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compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
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reg = <0x00a00400 0x100>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>;
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resets = <&usb_mod_clk 17>;
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clocks = <&usb_clocks CLK_BUS_HCI0>,
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<&usb_clocks CLK_USB_OHCI0>;
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resets = <&usb_clocks RST_USB0_HCI>;
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phys = <&usbphy1>;
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phy-names = "usb";
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status = "disabled";
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@ -474,9 +267,9 @@ ohci0: usb@00a00400 {
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usbphy1: phy@00a00800 {
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compatible = "allwinner,sun9i-a80-usb-phy";
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reg = <0x00a00800 0x4>;
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clocks = <&usb_phy_clk 1>;
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clocks = <&usb_clocks CLK_USB0_PHY>;
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clock-names = "phy";
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resets = <&usb_phy_clk 17>;
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resets = <&usb_clocks RST_USB0_PHY>;
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reset-names = "phy";
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status = "disabled";
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#phy-cells = <0>;
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@ -486,8 +279,8 @@ ehci1: usb@00a01000 {
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compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
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reg = <0x00a01000 0x100>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usb_mod_clk 3>;
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resets = <&usb_mod_clk 18>;
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clocks = <&usb_clocks CLK_BUS_HCI1>;
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resets = <&usb_clocks RST_USB1_HCI>;
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phys = <&usbphy2>;
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phy-names = "usb";
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status = "disabled";
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@ -496,11 +289,16 @@ ehci1: usb@00a01000 {
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usbphy2: phy@00a01800 {
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compatible = "allwinner,sun9i-a80-usb-phy";
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reg = <0x00a01800 0x4>;
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clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,
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<&usb_phy_clk 3>;
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clock-names = "hsic_480M", "hsic_12M", "phy";
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resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
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reset-names = "hsic", "phy";
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clocks = <&usb_clocks CLK_USB1_HSIC>,
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<&usb_clocks CLK_USB_HSIC>,
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<&usb_clocks CLK_USB1_PHY>;
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clock-names = "hsic_480M",
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"hsic_12M",
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"phy";
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resets = <&usb_clocks RST_USB1_HSIC>,
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<&usb_clocks RST_USB1_PHY>;
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reset-names = "hsic",
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"phy";
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status = "disabled";
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#phy-cells = <0>;
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/* usb1 is always used with HSIC */
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@ -511,8 +309,8 @@ ehci2: usb@00a02000 {
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compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
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reg = <0x00a02000 0x100>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usb_mod_clk 5>;
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resets = <&usb_mod_clk 19>;
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clocks = <&usb_clocks CLK_BUS_HCI2>;
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resets = <&usb_clocks RST_USB2_HCI>;
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phys = <&usbphy3>;
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phy-names = "usb";
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status = "disabled";
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@ -522,8 +320,9 @@ ohci2: usb@00a02400 {
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compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
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reg = <0x00a02400 0x100>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>;
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resets = <&usb_mod_clk 19>;
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clocks = <&usb_clocks CLK_BUS_HCI2>,
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<&usb_clocks CLK_USB_OHCI2>;
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resets = <&usb_clocks RST_USB2_HCI>;
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phys = <&usbphy3>;
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phy-names = "usb";
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status = "disabled";
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@ -532,20 +331,35 @@ ohci2: usb@00a02400 {
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usbphy3: phy@00a02800 {
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compatible = "allwinner,sun9i-a80-usb-phy";
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reg = <0x00a02800 0x4>;
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clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>,
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<&usb_phy_clk 5>;
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clock-names = "hsic_480M", "hsic_12M", "phy";
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resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>;
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reset-names = "hsic", "phy";
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clocks = <&usb_clocks CLK_USB2_HSIC>,
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<&usb_clocks CLK_USB_HSIC>,
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<&usb_clocks CLK_USB2_PHY>;
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clock-names = "hsic_480M",
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"hsic_12M",
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"phy";
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resets = <&usb_clocks RST_USB2_HSIC>,
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<&usb_clocks RST_USB2_PHY>;
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reset-names = "hsic",
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"phy";
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status = "disabled";
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#phy-cells = <0>;
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};
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usb_clocks: clock@00a08000 {
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compatible = "allwinner,sun9i-a80-usb-clks";
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reg = <0x00a08000 0x8>;
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clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
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clock-names = "bus", "hosc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun9i-a80-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
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<&mmc0_clk 1>, <&mmc0_clk 2>;
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clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
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<&ccu CLK_MMC0_OUTPUT>,
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<&ccu CLK_MMC0_SAMPLE>;
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clock-names = "ahb", "mmc", "output", "sample";
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resets = <&mmc_config_clk 0>;
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reset-names = "ahb";
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@ -558,8 +372,9 @@ mmc0: mmc@01c0f000 {
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mmc1: mmc@01c10000 {
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compatible = "allwinner,sun9i-a80-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
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<&mmc1_clk 1>, <&mmc1_clk 2>;
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clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
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||||
<&ccu CLK_MMC1_OUTPUT>,
|
||||
<&ccu CLK_MMC1_SAMPLE>;
|
||||
clock-names = "ahb", "mmc", "output", "sample";
|
||||
resets = <&mmc_config_clk 1>;
|
||||
reset-names = "ahb";
|
||||
|
|
@ -572,8 +387,9 @@ mmc1: mmc@01c10000 {
|
|||
mmc2: mmc@01c11000 {
|
||||
compatible = "allwinner,sun9i-a80-mmc";
|
||||
reg = <0x01c11000 0x1000>;
|
||||
clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
|
||||
<&mmc2_clk 1>, <&mmc2_clk 2>;
|
||||
clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
|
||||
<&ccu CLK_MMC2_OUTPUT>,
|
||||
<&ccu CLK_MMC2_SAMPLE>;
|
||||
clock-names = "ahb", "mmc", "output", "sample";
|
||||
resets = <&mmc_config_clk 2>;
|
||||
reset-names = "ahb";
|
||||
|
|
@ -586,8 +402,9 @@ mmc2: mmc@01c11000 {
|
|||
mmc3: mmc@01c12000 {
|
||||
compatible = "allwinner,sun9i-a80-mmc";
|
||||
reg = <0x01c12000 0x1000>;
|
||||
clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
|
||||
<&mmc3_clk 1>, <&mmc3_clk 2>;
|
||||
clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
|
||||
<&ccu CLK_MMC3_OUTPUT>,
|
||||
<&ccu CLK_MMC3_SAMPLE>;
|
||||
clock-names = "ahb", "mmc", "output", "sample";
|
||||
resets = <&mmc_config_clk 3>;
|
||||
reset-names = "ahb";
|
||||
|
|
@ -600,9 +417,9 @@ mmc3: mmc@01c12000 {
|
|||
mmc_config_clk: clk@01c13000 {
|
||||
compatible = "allwinner,sun9i-a80-mmc-config-clk";
|
||||
reg = <0x01c13000 0x10>;
|
||||
clocks = <&ahb0_gates 8>;
|
||||
clocks = <&ccu CLK_BUS_MMC>;
|
||||
clock-names = "ahb";
|
||||
resets = <&ahb0_resets 8>;
|
||||
resets = <&ccu RST_BUS_MMC>;
|
||||
reset-names = "ahb";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
|
@ -621,34 +438,27 @@ gic: interrupt-controller@01c41000 {
|
|||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
ahb0_resets: reset@060005a0 {
|
||||
de_clocks: clock@03000000 {
|
||||
compatible = "allwinner,sun9i-a80-de-clks";
|
||||
reg = <0x03000000 0x30>;
|
||||
clocks = <&ccu CLK_DE>,
|
||||
<&ccu CLK_SDRAM>,
|
||||
<&ccu CLK_BUS_DE>;
|
||||
clock-names = "mod",
|
||||
"dram",
|
||||
"bus";
|
||||
resets = <&ccu RST_BUS_DE>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun6i-a31-clock-reset";
|
||||
reg = <0x060005a0 0x4>;
|
||||
};
|
||||
|
||||
ahb1_resets: reset@060005a4 {
|
||||
ccu: clock@06000000 {
|
||||
compatible = "allwinner,sun9i-a80-ccu";
|
||||
reg = <0x06000000 0x800>;
|
||||
clocks = <&osc24M>, <&osc32k>;
|
||||
clock-names = "hosc", "losc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun6i-a31-clock-reset";
|
||||
reg = <0x060005a4 0x4>;
|
||||
};
|
||||
|
||||
ahb2_resets: reset@060005a8 {
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun6i-a31-clock-reset";
|
||||
reg = <0x060005a8 0x4>;
|
||||
};
|
||||
|
||||
apb0_resets: reset@060005b0 {
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun6i-a31-clock-reset";
|
||||
reg = <0x060005b0 0x4>;
|
||||
};
|
||||
|
||||
apb1_resets: reset@060005b4 {
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun6i-a31-clock-reset";
|
||||
reg = <0x060005b4 0x4>;
|
||||
};
|
||||
|
||||
timer@06000c00 {
|
||||
|
|
@ -678,7 +488,7 @@ pio: pinctrl@06000800 {
|
|||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
|
||||
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
|
||||
clock-names = "apb", "hosc", "losc";
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
|
|
@ -740,8 +550,8 @@ uart0: serial@07000000 {
|
|||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 16>;
|
||||
resets = <&apb1_resets 16>;
|
||||
clocks = <&ccu CLK_BUS_UART0>;
|
||||
resets = <&ccu RST_BUS_UART0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -751,8 +561,8 @@ uart1: serial@07000400 {
|
|||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 17>;
|
||||
resets = <&apb1_resets 17>;
|
||||
clocks = <&ccu CLK_BUS_UART1>;
|
||||
resets = <&ccu RST_BUS_UART1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -762,8 +572,8 @@ uart2: serial@07000800 {
|
|||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 18>;
|
||||
resets = <&apb1_resets 18>;
|
||||
clocks = <&ccu CLK_BUS_UART2>;
|
||||
resets = <&ccu RST_BUS_UART2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -773,8 +583,8 @@ uart3: serial@07000c00 {
|
|||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 19>;
|
||||
resets = <&apb1_resets 19>;
|
||||
clocks = <&ccu CLK_BUS_UART3>;
|
||||
resets = <&ccu RST_BUS_UART3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -784,8 +594,8 @@ uart4: serial@07001000 {
|
|||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 20>;
|
||||
resets = <&apb1_resets 20>;
|
||||
clocks = <&ccu CLK_BUS_UART4>;
|
||||
resets = <&ccu RST_BUS_UART4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -795,8 +605,8 @@ uart5: serial@07001400 {
|
|||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 21>;
|
||||
resets = <&apb1_resets 21>;
|
||||
clocks = <&ccu CLK_BUS_UART5>;
|
||||
resets = <&ccu RST_BUS_UART5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -804,8 +614,8 @@ i2c0: i2c@07002800 {
|
|||
compatible = "allwinner,sun6i-a31-i2c";
|
||||
reg = <0x07002800 0x400>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 0>;
|
||||
resets = <&apb1_resets 0>;
|
||||
clocks = <&ccu CLK_BUS_I2C0>;
|
||||
resets = <&ccu RST_BUS_I2C0>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -815,8 +625,8 @@ i2c1: i2c@07002c00 {
|
|||
compatible = "allwinner,sun6i-a31-i2c";
|
||||
reg = <0x07002c00 0x400>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 1>;
|
||||
resets = <&apb1_resets 1>;
|
||||
clocks = <&ccu CLK_BUS_I2C1>;
|
||||
resets = <&ccu RST_BUS_I2C1>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -826,8 +636,8 @@ i2c2: i2c@07003000 {
|
|||
compatible = "allwinner,sun6i-a31-i2c";
|
||||
reg = <0x07003000 0x400>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 2>;
|
||||
resets = <&apb1_resets 2>;
|
||||
clocks = <&ccu CLK_BUS_I2C2>;
|
||||
resets = <&ccu RST_BUS_I2C2>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -837,8 +647,8 @@ i2c3: i2c@07003400 {
|
|||
compatible = "allwinner,sun6i-a31-i2c";
|
||||
reg = <0x07003400 0x400>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 3>;
|
||||
resets = <&apb1_resets 3>;
|
||||
clocks = <&ccu CLK_BUS_I2C3>;
|
||||
resets = <&ccu RST_BUS_I2C3>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -848,8 +658,8 @@ i2c4: i2c@07003800 {
|
|||
compatible = "allwinner,sun6i-a31-i2c";
|
||||
reg = <0x07003800 0x400>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 4>;
|
||||
resets = <&apb1_resets 4>;
|
||||
clocks = <&ccu CLK_BUS_I2C4>;
|
||||
resets = <&ccu RST_BUS_I2C4>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue