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coresight tmc: Add support for Coresight SoC 600 TMC
The coresight SoC 600 supports ETR save-restore which allows us to restore a trace session by retaining the RRP/RWP/STS.Full values when the TMC leaves the Disabled state. However, the TMC doesn't have a scatter-gather unit in built. Also, TMCs have different PIDs in different configurations (ETF, ETB & ETR), unlike the previous generation. While the DEVID exposes some of the features/changes in the TMC, it doesn't explicitly advertises the new save-restore feature as described above. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -442,6 +442,22 @@ static struct amba_id tmc_ids[] = {
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.id = 0x0003b961,
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.mask = 0x0003ffff,
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},
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{
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/* Coresight SoC 600 TMC-ETR/ETS */
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.id = 0x000bb9e8,
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.mask = 0x000fffff,
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.data = (void *)(unsigned long)CORESIGHT_SOC_600_ETR_CAPS,
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},
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{
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/* Coresight SoC 600 TMC-ETB */
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.id = 0x000bb9e9,
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.mask = 0x000fffff,
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},
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{
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/* Coresight SoC 600 TMC-ETF */
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.id = 0x000bb9ea,
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.mask = 0x000fffff,
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},
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{ 0, 0},
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};
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@ -129,6 +129,10 @@ enum tmc_mem_intf_width {
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*/
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#define TMC_ETR_SAVE_RESTORE (0x1U << 2)
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/* Coresight SoC-600 TMC-ETR unadvertised capabilities */
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#define CORESIGHT_SOC_600_ETR_CAPS \
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(TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
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/**
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* struct tmc_drvdata - specifics associated to an TMC component
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* @base: memory mapped base address for this component.
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