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drm/amd/display: Added negative check for vertical line start. 

In case of vstartup happens before vsync, set vertical line
	start to 0.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yongqiang Sun 2017-08-30 11:55:40 -04:00 committed by Alex Deucher
parent 6f54d0b1d8
commit 649e0c7679
1 changed files with 7 additions and 3 deletions
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10
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
View File

@ -118,7 +118,7 @@ static void tgn10_program_timing(
uint32_t start_point = 0;
uint32_t field_num = 0;
uint32_t h_div_2;
uint32_t vertial_line_start;
int32_t vertical_line_start;
struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
@ -216,9 +216,13 @@ static void tgn10_program_timing(
/* Use OTG_VERTICAL_INTERRUPT2 replace VUPDATE interrupt,
* program the reg for interrupt postition.
*/
vertial_line_start = asic_blank_end - tg->dlg_otg_param.vstartup_start + 1;
vertical_line_start = asic_blank_end - tg->dlg_otg_param.vstartup_start + 1;
if (vertical_line_start < 0) {
ASSERT(0);
vertical_line_start = 0;
}
REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
OTG_VERTICAL_INTERRUPT2_LINE_START, vertial_line_start);
OTG_VERTICAL_INTERRUPT2_LINE_START, vertical_line_start);
/* v_sync polarity */
v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?