From a16761acd9d209328210678c76ffba478af8c731 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Date: Thu, 27 Feb 2014 22:28:02 +0100 Subject: [PATCH 1/8] ARM: dove: add system controller node This adds a DT node for the system-controller found on Marvell Dove SoCs. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> --- arch/arm/boot/dts/dove.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 43cbdc2366b3..b6fc27f8ed66 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -186,6 +186,11 @@ mbusc: mbus-ctrl@20000 { reg = <0x20000 0x80>, <0x800100 0x8>; }; + sysc: system-ctrl@20000 { + compatible = "marvell,orion-system-controller"; + reg = <0x20000 0x110>; + }; + bridge_intc: bridge-interrupt-ctrl@20110 { compatible = "marvell,orion-bridge-intc"; interrupt-controller; From 46febc63669b23a8e8a7e4daa1341bc198130098 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Date: Tue, 4 Mar 2014 17:36:59 +0100 Subject: [PATCH 2/8] ARM: mvebu: change the default PCIe apertures for Armada 370/XP The latest Marvell bootloaders for various boards change the MBus Window base address from 0xC0000000 to 0xF0000000, in order to make more RAM in the first 4 GB actually usable by the kernel (RAM that is covered by the MBus window is "shadowed" and therefore not usable). However, our default PCIe memory and I/O apertures where sitting at 0xe0000000 (for memory) and 0xe8000000 (for I/O), which will now be outside of the MBus Window range on those platforms. To make things work, we have to ensure those apertures use addresses in the 0xF0000000 -> 0xFFFFFFFF range. Of course this change of the MBus Window base address from 0xC0000000 to 0xF0000000 also comes with a change of the internal register base address from 0xD0000000 to 0xF1000000. We have therefore designed the following memory map: * 0xF0000000 -> 0xF1000000: 16 MB, used for NOR flashes on Armada XP GP and Armada XP DB. * 0xF1000000 -> 0xF1100000: 1 MB, used for internal registers. * 0xF8000000 -> 0xFFE00000: 126 MB, used for PCIe memory. * 0xFFE00000 -> 0xFFF00000: 1 MB, used for PCIe I/O. * 0xFFF00000 -> 0xFFFFFFFF: 1 MB, used for the BootROM mapping There is one exception to this layout: the Armada XP OpenBlocks, which has a 128 MB NOR flash, mapped from 0xF0000000 to 0xF8000000. This does not conflict with the current change for the PCIe I/O and memory apertures, and continues to work because on Armada XP OpenBlocks, the bootloader is an old one, and continues to have internal registers mapped at 0xD0000000. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> --- arch/arm/boot/dts/armada-370-xp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 7bbc4ac997fb..bbb40f62037d 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -44,8 +44,8 @@ soc { #size-cells = <1>; controller = <&mbusc>; interrupt-parent = <&mpic>; - pcie-mem-aperture = <0xe0000000 0x8000000>; - pcie-io-aperture = <0xe8000000 0x100000>; + pcie-mem-aperture = <0xf8000000 0x7e00000>; + pcie-io-aperture = <0xffe00000 0x100000>; devbus-bootcs { compatible = "marvell,mvebu-devbus"; From 82066bdb5a759ec00c18f9667853c4fe8840e83d Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Date: Tue, 4 Mar 2014 17:37:00 +0100 Subject: [PATCH 3/8] ARM: mvebu: switch the Armada XP DB to use internal registers at 0xf1000000 Marvell has now provided bootloaders that are Device Tree capable for the Armada XP DB board, and that also remap the internal register base address to 0xf1000000. In addition, the bootloader now sets the MBus Window base address to 0xf0000000, but on this board, this change doesn't make much difference since the board is by default equipped with 2 GB of RAM. Therefore this commit updates the soc->ranges Device Tree property with the fact that the internal registers are now mapped at 0xf1000000. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> --- arch/arm/boot/dts/armada-xp-db.dts | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index bcf6d79a57ec..448373c4b0e5 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -2,7 +2,7 @@ * Device Tree file for Marvell Armada XP evaluation board * (DB-78460-BP) * - * Copyright (C) 2012 Marvell + * Copyright (C) 2012-2014 Marvell * * Lior Amsalem <alior@marvell.com> * Gregory CLEMENT <gregory.clement@free-electrons.com> @@ -11,6 +11,15 @@ * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. */ /dts-v1/; @@ -30,7 +39,7 @@ memory { }; soc { - ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; From 91ed32200e6ea1df19df01355c5c7747f9014102 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Date: Tue, 4 Mar 2014 17:37:01 +0100 Subject: [PATCH 4/8] ARM: mvebu: switch the Armada XP GP to use internal registers at 0xf1000000 Marvell has now provided bootloaders that are Device Tree capable for the Armada XP GP board, and that also remap the internal register base address to 0xf1000000. In addition, the bootloader now sets the MBus Window base address to 0xf0000000, which allows to use much more RAM in the last GB of RAM before the 4 GB limit (the entire space from 0xC0000000 to 0xFFFFFFFF was not usable due to being used for I/O, not only the space from 0xF0000000 to 0xFFFFFFFF is used for I/O). Therefore this commit: * Updates the memory->reg Device Tree property with the fact that in the first bank of RAM, memory up to 0xf0000000 can be used. * Updates the soc->ranges Device Tree property with the fact that the internal registers are now mapped at 0xf1000000. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> --- arch/arm/boot/dts/armada-xp-gp.dts | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 274e2ad5f51c..61bda687f782 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -2,7 +2,7 @@ * Device Tree file for Marvell Armada XP development board * (DB-MV784MP-GP) * - * Copyright (C) 2013 Marvell + * Copyright (C) 2013-2014 Marvell * * Lior Amsalem <alior@marvell.com> * Gregory CLEMENT <gregory.clement@free-electrons.com> @@ -11,6 +11,15 @@ * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. */ /dts-v1/; @@ -30,16 +39,17 @@ memory { * 8 GB of plug-in RAM modules by default.The amount * of memory available can be changed by the * bootloader according the size of the module - * actually plugged. Only 7GB are usable because - * addresses from 0xC0000000 to 0xffffffff are used by - * the internal registers of the SoC. + * actually plugged. However, memory between + * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is + * the address range used for I/O (internal registers, + * MBus windows). */ - reg = <0x00000000 0x00000000 0x00000000 0xC0000000>, + reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, <0x00000001 0x00000000 0x00000001 0x00000000>; }; soc { - ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; From ebe021e2688a1f6aaa092f8ea6e72899a2c61a91 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Date: Tue, 4 Mar 2014 17:37:02 +0100 Subject: [PATCH 5/8] ARM: mvebu: the Armada XP Matrix board has 4 GB Since the Armada XP Matrix board has 4 GB of RAM and not 2 GB, we update the Device Tree to take into account the correct amount of memory. As noted in the new comment, the last 256 MB of RAM are in fact not usable, due to the overlap with the MBus Window address range. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> --- arch/arm/boot/dts/armada-xp-matrix.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts index e47c49ecd55c..c2242745b9b8 100644 --- a/arch/arm/boot/dts/armada-xp-matrix.dts +++ b/arch/arm/boot/dts/armada-xp-matrix.dts @@ -23,7 +23,12 @@ chosen { memory { device_type = "memory"; - reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ + /* + * This board has 4 GB of RAM, but the last 256 MB of + * RAM are not usable due to the overlap with the MBus + * Window address range + */ + reg = <0 0x00000000 0 0xf0000000>; }; soc { From 0d2e63782cd2ce0a987ffc73f3b2c4afe8375f4c Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Date: Thu, 6 Mar 2014 15:41:55 +0100 Subject: [PATCH 6/8] ARM: mvebu: use the correct phy connection mode on Armada 385 DB On Armada 385 DB, while the "rgmii" PHY connection mode works fine with the generic PHY driver, it fails to work when the Marvell PHY driver is enabled in the kernel configuration, due to a finer handling of the PHY configuration. This is due to the fact that the phy connection mode should instead be "rgmii-id", i.e with the TX/RX delay mechanisms enabled. This fixes the network operation on Armada 385 DB with CONFIG_MARVELL_PHY=y. Without this patch and this option enabled, one would only get messages such as: mvneta f1070000.ethernet eth1: bad rx status 0cc10000 (crc error), size=70 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> --- arch/arm/boot/dts/armada-385-db.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts index 01b6cc76ddc8..9a136428ec29 100644 --- a/arch/arm/boot/dts/armada-385-db.dts +++ b/arch/arm/boot/dts/armada-385-db.dts @@ -62,13 +62,13 @@ serial@12000 { ethernet@30000 { status = "okay"; phy = <&phy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; ethernet@70000 { status = "okay"; phy = <&phy0>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; mdio { From a8a921dd22778bd0b093700957eff4fd1649eb28 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT <gregory.clement@free-electrons.com> Date: Thu, 6 Mar 2014 16:17:55 +0100 Subject: [PATCH 7/8] ARM: mvebu: add Device Tree for the Armada 385 RD board The Armada 385 RD board is the reference design board from Marvell for the Armada 385 SoC. This commit adds a Device Tree description for this board, which enables the following features: * Network interfaces * I2C bus * Serial port * SPI bus, with a SPI flash * PCIe interface Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/armada-385-rd.dts | 94 +++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/armada-385-rd.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a292b3cc94a5..52c501b0415b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -152,7 +152,8 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \ dtb-$(CONFIG_MACH_ARMADA_375) += \ armada-375-db.dtb dtb-$(CONFIG_MACH_ARMADA_38X) += \ - armada-385-db.dtb + armada-385-db.dtb \ + armada-385-rd.dtb dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-axpwifiap.dtb \ armada-xp-db.dtb \ diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts new file mode 100644 index 000000000000..45250c88814b --- /dev/null +++ b/arch/arm/boot/dts/armada-385-rd.dts @@ -0,0 +1,94 @@ +/* + * Device Tree file for Marvell Armada 385 Reference Design board + * (RD-88F6820-AP) + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +#include "armada-385.dtsi" + +/ { + model = "Marvell Armada 385 Reference Design"; + compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; /* 256 MB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; + + internal-regs { + spi@10600 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + }; + + serial@12000 { + clock-frequency = <200000000>; + status = "okay"; + }; + + ethernet@30000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + pcie-controller { + status = "okay"; + /* + * One PCIe units is accessible through + * standard PCIe slot on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + }; + }; +}; From df76299fecb3d921e4762ae540e33d8b9b1c3c1e Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Date: Wed, 5 Mar 2014 01:03:08 +0100 Subject: [PATCH 8/8] ARM: dove: drop pinctrl PMU reg property Marvell Dove's pinctrl does require some PMU regs for muxing PMU functions to MPP pins. Recently, a discussion started about consolidating Power Management Unit (PMU) into a single DT node. As we don't want anymore DT ABI in the way, drop the corresponding reg property from pinctrl node now. The driver will derive the registers from existing reg properties. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net> --- arch/arm/boot/dts/dove.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index b6fc27f8ed66..3b891dd20993 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -395,8 +395,7 @@ gate_clk: clock-gating-ctrl@d0038 { pinctrl: pin-ctrl@d0200 { compatible = "marvell,dove-pinctrl"; reg = <0xd0200 0x14>, - <0xd0440 0x04>, - <0xd802c 0x08>; + <0xd0440 0x04>; clocks = <&gate_clk 22>; pmx_gpio_0: pmx-gpio-0 {