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Staging: w35und: wb35reg struct typedef removal 

This patch removes the WB35REG struct typedefs and fixes up variable names that
use the type.

Signed-off-by: Pekka Enberg <penberg@cs.helsinki.fi>
Acked-by: Pavel Machek <pavel@suse.cz>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Pekka Enberg 2008-10-22 11:02:37 +03:00 committed by Greg Kroah-Hartman
parent f37435ce86
commit 65144de798
6 changed files with 406 additions and 407 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

262
drivers/staging/winbond/linux/wb35reg.c
View File

@ -12,7 +12,7 @@ extern void phy_calibration_winbond(hw_data_t *phw_data, u32 frequency);
unsigned char
Wb35Reg_BurstWrite(phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterData, u8 NumberOfData, u8 Flag)
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
struct urb *urb = NULL;
struct wb35_reg_queue *reg_queue = NULL;
u16 UrbSize;
@ -46,14 +46,14 @@ Wb35Reg_BurstWrite(phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterData, u8 N
reg_queue->pUsbReq = dr;
reg_queue->urb = urb;
spin_lock_irq( &pWb35Reg->EP0VM_spin_lock );
if (pWb35Reg->reg_first == NULL)
pWb35Reg->reg_first = reg_queue;
spin_lock_irq( &reg->EP0VM_spin_lock );
if (reg->reg_first == NULL)
reg->reg_first = reg_queue;
else
pWb35Reg->reg_last->Next = reg_queue;
pWb35Reg->reg_last = reg_queue;
reg->reg_last->Next = reg_queue;
reg->reg_last = reg_queue;
spin_unlock_irq( &pWb35Reg->EP0VM_spin_lock );
spin_unlock_irq( &reg->EP0VM_spin_lock );
// Start EP0VM
Wb35Reg_EP0VM_start(pHwData);
@ -72,43 +72,43 @@ Wb35Reg_BurstWrite(phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterData, u8 N
void
Wb35Reg_Update(phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue)
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
switch (RegisterNo) {
case 0x3b0: pWb35Reg->U1B0 = RegisterValue; break;
case 0x3bc: pWb35Reg->U1BC_LEDConfigure = RegisterValue; break;
case 0x400: pWb35Reg->D00_DmaControl = RegisterValue; break;
case 0x800: pWb35Reg->M00_MacControl = RegisterValue; break;
case 0x804: pWb35Reg->M04_MulticastAddress1 = RegisterValue; break;
case 0x808: pWb35Reg->M08_MulticastAddress2 = RegisterValue; break;
case 0x824: pWb35Reg->M24_MacControl = RegisterValue; break;
case 0x828: pWb35Reg->M28_MacControl = RegisterValue; break;
case 0x82c: pWb35Reg->M2C_MacControl = RegisterValue; break;
case 0x838: pWb35Reg->M38_MacControl = RegisterValue; break;
case 0x840: pWb35Reg->M40_MacControl = RegisterValue; break;
case 0x844: pWb35Reg->M44_MacControl = RegisterValue; break;
case 0x848: pWb35Reg->M48_MacControl = RegisterValue; break;
case 0x84c: pWb35Reg->M4C_MacStatus = RegisterValue; break;
case 0x860: pWb35Reg->M60_MacControl = RegisterValue; break;
case 0x868: pWb35Reg->M68_MacControl = RegisterValue; break;
case 0x870: pWb35Reg->M70_MacControl = RegisterValue; break;
case 0x874: pWb35Reg->M74_MacControl = RegisterValue; break;
case 0x878: pWb35Reg->M78_ERPInformation = RegisterValue; break;
case 0x87C: pWb35Reg->M7C_MacControl = RegisterValue; break;
case 0x880: pWb35Reg->M80_MacControl = RegisterValue; break;
case 0x884: pWb35Reg->M84_MacControl = RegisterValue; break;
case 0x888: pWb35Reg->M88_MacControl = RegisterValue; break;
case 0x898: pWb35Reg->M98_MacControl = RegisterValue; break;
case 0x100c: pWb35Reg->BB0C = RegisterValue; break;
case 0x102c: pWb35Reg->BB2C = RegisterValue; break;
case 0x1030: pWb35Reg->BB30 = RegisterValue; break;
case 0x103c: pWb35Reg->BB3C = RegisterValue; break;
case 0x1048: pWb35Reg->BB48 = RegisterValue; break;
case 0x104c: pWb35Reg->BB4C = RegisterValue; break;
case 0x1050: pWb35Reg->BB50 = RegisterValue; break;
case 0x1054: pWb35Reg->BB54 = RegisterValue; break;
case 0x1058: pWb35Reg->BB58 = RegisterValue; break;
case 0x105c: pWb35Reg->BB5C = RegisterValue; break;
case 0x1060: pWb35Reg->BB60 = RegisterValue; break;
case 0x3b0: reg->U1B0 = RegisterValue; break;
case 0x3bc: reg->U1BC_LEDConfigure = RegisterValue; break;
case 0x400: reg->D00_DmaControl = RegisterValue; break;
case 0x800: reg->M00_MacControl = RegisterValue; break;
case 0x804: reg->M04_MulticastAddress1 = RegisterValue; break;
case 0x808: reg->M08_MulticastAddress2 = RegisterValue; break;
case 0x824: reg->M24_MacControl = RegisterValue; break;
case 0x828: reg->M28_MacControl = RegisterValue; break;
case 0x82c: reg->M2C_MacControl = RegisterValue; break;
case 0x838: reg->M38_MacControl = RegisterValue; break;
case 0x840: reg->M40_MacControl = RegisterValue; break;
case 0x844: reg->M44_MacControl = RegisterValue; break;
case 0x848: reg->M48_MacControl = RegisterValue; break;
case 0x84c: reg->M4C_MacStatus = RegisterValue; break;
case 0x860: reg->M60_MacControl = RegisterValue; break;
case 0x868: reg->M68_MacControl = RegisterValue; break;
case 0x870: reg->M70_MacControl = RegisterValue; break;
case 0x874: reg->M74_MacControl = RegisterValue; break;
case 0x878: reg->M78_ERPInformation = RegisterValue; break;
case 0x87C: reg->M7C_MacControl = RegisterValue; break;
case 0x880: reg->M80_MacControl = RegisterValue; break;
case 0x884: reg->M84_MacControl = RegisterValue; break;
case 0x888: reg->M88_MacControl = RegisterValue; break;
case 0x898: reg->M98_MacControl = RegisterValue; break;
case 0x100c: reg->BB0C = RegisterValue; break;
case 0x102c: reg->BB2C = RegisterValue; break;
case 0x1030: reg->BB30 = RegisterValue; break;
case 0x103c: reg->BB3C = RegisterValue; break;
case 0x1048: reg->BB48 = RegisterValue; break;
case 0x104c: reg->BB4C = RegisterValue; break;
case 0x1050: reg->BB50 = RegisterValue; break;
case 0x1054: reg->BB54 = RegisterValue; break;
case 0x1058: reg->BB58 = RegisterValue; break;
case 0x105c: reg->BB5C = RegisterValue; break;
case 0x1060: reg->BB60 = RegisterValue; break;
}
}
@ -117,7 +117,7 @@ Wb35Reg_Update(phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue)
unsigned char
Wb35Reg_WriteSync( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
int ret = -1;
// Module shutdown
@ -127,20 +127,20 @@ Wb35Reg_WriteSync( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue )
RegisterValue = cpu_to_le32(RegisterValue);
// update the register by send usb message------------------------------------
pWb35Reg->SyncIoPause = 1;
reg->SyncIoPause = 1;
// 20060717.5 Wait until EP0VM stop
while (pWb35Reg->EP0vm_state != VM_STOP)
while (reg->EP0vm_state != VM_STOP)
msleep(10);
// Sync IoCallDriver
pWb35Reg->EP0vm_state = VM_RUNNING;
reg->EP0vm_state = VM_RUNNING;
ret = usb_control_msg( pHwData->WbUsb.udev,
usb_sndctrlpipe( pHwData->WbUsb.udev, 0 ),
0x03, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
0x0,RegisterNo, &RegisterValue, 4, HZ*100 );
pWb35Reg->EP0vm_state = VM_STOP;
pWb35Reg->SyncIoPause = 0;
reg->EP0vm_state = VM_STOP;
reg->SyncIoPause = 0;
Wb35Reg_EP0VM_start(pHwData);
@ -161,7 +161,7 @@ Wb35Reg_WriteSync( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue )
unsigned char
Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
struct usb_ctrlrequest *dr;
struct urb *urb = NULL;
struct wb35_reg_queue *reg_queue = NULL;
@ -193,14 +193,14 @@ Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue )
reg_queue->pUsbReq = dr;
reg_queue->urb = urb;
spin_lock_irq(&pWb35Reg->EP0VM_spin_lock );
if (pWb35Reg->reg_first == NULL)
pWb35Reg->reg_first = reg_queue;
spin_lock_irq(&reg->EP0VM_spin_lock );
if (reg->reg_first == NULL)
reg->reg_first = reg_queue;
else
pWb35Reg->reg_last->Next = reg_queue;
pWb35Reg->reg_last = reg_queue;
reg->reg_last->Next = reg_queue;
reg->reg_last = reg_queue;
spin_unlock_irq( &pWb35Reg->EP0VM_spin_lock );
spin_unlock_irq( &reg->EP0VM_spin_lock );
// Start EP0VM
Wb35Reg_EP0VM_start(pHwData);
@ -222,7 +222,7 @@ unsigned char
Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue,
s8 *pValue, s8 Len)
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
struct usb_ctrlrequest *dr;
struct urb *urb = NULL;
struct wb35_reg_queue *reg_queue = NULL;
@ -254,14 +254,14 @@ Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData, u16 RegisterNo, u32 Register
reg_queue->Next = NULL;
reg_queue->pUsbReq = dr;
reg_queue->urb = urb;
spin_lock_irq (&pWb35Reg->EP0VM_spin_lock );
if( pWb35Reg->reg_first == NULL )
pWb35Reg->reg_first = reg_queue;
spin_lock_irq (&reg->EP0VM_spin_lock );
if( reg->reg_first == NULL )
reg->reg_first = reg_queue;
else
pWb35Reg->reg_last->Next = reg_queue;
pWb35Reg->reg_last = reg_queue;
reg->reg_last->Next = reg_queue;
reg->reg_last = reg_queue;
spin_unlock_irq ( &pWb35Reg->EP0VM_spin_lock );
spin_unlock_irq ( &reg->EP0VM_spin_lock );
// Start EP0VM
Wb35Reg_EP0VM_start(pHwData);
@ -280,7 +280,7 @@ Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData, u16 RegisterNo, u32 Register
unsigned char
Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
u32 * pltmp = pRegisterValue;
int ret = -1;
@ -290,13 +290,13 @@ Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue )
// Read the register by send usb message------------------------------------
pWb35Reg->SyncIoPause = 1;
reg->SyncIoPause = 1;
// 20060717.5 Wait until EP0VM stop
while (pWb35Reg->EP0vm_state != VM_STOP)
while (reg->EP0vm_state != VM_STOP)
msleep(10);
pWb35Reg->EP0vm_state = VM_RUNNING;
reg->EP0vm_state = VM_RUNNING;
ret = usb_control_msg( pHwData->WbUsb.udev,
usb_rcvctrlpipe(pHwData->WbUsb.udev, 0),
0x01, USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN,
@ -304,10 +304,10 @@ Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue )
*pRegisterValue = cpu_to_le32(*pltmp);
pWb35Reg->EP0vm_state = VM_STOP;
reg->EP0vm_state = VM_STOP;
Wb35Reg_Update( pHwData, RegisterNo, *pRegisterValue );
pWb35Reg->SyncIoPause = 0;
reg->SyncIoPause = 0;
Wb35Reg_EP0VM_start( pHwData );
@ -329,7 +329,7 @@ Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue )
unsigned char
Wb35Reg_Read(phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
struct usb_ctrlrequest * dr;
struct urb *urb;
struct wb35_reg_queue *reg_queue;
@ -359,14 +359,14 @@ Wb35Reg_Read(phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue )
reg_queue->Next = NULL;
reg_queue->pUsbReq = dr;
reg_queue->urb = urb;
spin_lock_irq ( &pWb35Reg->EP0VM_spin_lock );
if( pWb35Reg->reg_first == NULL )
pWb35Reg->reg_first = reg_queue;
spin_lock_irq ( &reg->EP0VM_spin_lock );
if( reg->reg_first == NULL )
reg->reg_first = reg_queue;
else
pWb35Reg->reg_last->Next = reg_queue;
pWb35Reg->reg_last = reg_queue;
reg->reg_last->Next = reg_queue;
reg->reg_last = reg_queue;
spin_unlock_irq( &pWb35Reg->EP0VM_spin_lock );
spin_unlock_irq( &reg->EP0VM_spin_lock );
// Start EP0VM
Wb35Reg_EP0VM_start( pHwData );
@ -384,19 +384,19 @@ Wb35Reg_Read(phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue )
void
Wb35Reg_EP0VM_start( phw_data_t pHwData )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
if (OS_ATOMIC_INC( pHwData->Adapter, &pWb35Reg->RegFireCount) == 1) {
pWb35Reg->EP0vm_state = VM_RUNNING;
if (OS_ATOMIC_INC( pHwData->Adapter, &reg->RegFireCount) == 1) {
reg->EP0vm_state = VM_RUNNING;
Wb35Reg_EP0VM(pHwData);
} else
OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Reg->RegFireCount );
OS_ATOMIC_DEC( pHwData->Adapter, &reg->RegFireCount );
}
void
Wb35Reg_EP0VM(phw_data_t pHwData )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
struct urb *urb;
struct usb_ctrlrequest *dr;
u32 * pBuffer;
@ -404,16 +404,16 @@ Wb35Reg_EP0VM(phw_data_t pHwData )
struct wb35_reg_queue *reg_queue;
if (pWb35Reg->SyncIoPause)
if (reg->SyncIoPause)
goto cleanup;
if (pHwData->SurpriseRemove)
goto cleanup;
// Get the register data and send to USB through Irp
spin_lock_irq( &pWb35Reg->EP0VM_spin_lock );
reg_queue = pWb35Reg->reg_first;
spin_unlock_irq( &pWb35Reg->EP0VM_spin_lock );
spin_lock_irq( &reg->EP0VM_spin_lock );
reg_queue = reg->reg_first;
spin_unlock_irq( &reg->EP0VM_spin_lock );
if (!reg_queue)
goto cleanup;
@ -432,7 +432,7 @@ Wb35Reg_EP0VM(phw_data_t pHwData )
(u8 *)dr,pBuffer,cpu_to_le16(dr->wLength),
Wb35Reg_EP0VM_complete, (void*)pHwData);
pWb35Reg->EP0vm_state = VM_RUNNING;
reg->EP0vm_state = VM_RUNNING;
ret = wb_usb_submit_urb( urb );
@ -446,8 +446,8 @@ Wb35Reg_EP0VM(phw_data_t pHwData )
return;
cleanup:
pWb35Reg->EP0vm_state = VM_STOP;
OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Reg->RegFireCount );
reg->EP0vm_state = VM_STOP;
OS_ATOMIC_DEC( pHwData->Adapter, &reg->RegFireCount );
}
@ -455,32 +455,32 @@ void
Wb35Reg_EP0VM_complete(struct urb *urb)
{
phw_data_t pHwData = (phw_data_t)urb->context;
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
struct wb35_reg_queue *reg_queue;
// Variable setting
pWb35Reg->EP0vm_state = VM_COMPLETED;
pWb35Reg->EP0VM_status = urb->status;
reg->EP0vm_state = VM_COMPLETED;
reg->EP0VM_status = urb->status;
if (pHwData->SurpriseRemove) { // Let WbWlanHalt to handle surprise remove
pWb35Reg->EP0vm_state = VM_STOP;
OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Reg->RegFireCount );
reg->EP0vm_state = VM_STOP;
OS_ATOMIC_DEC( pHwData->Adapter, &reg->RegFireCount );
} else {
// Complete to send, remove the URB from the first
spin_lock_irq( &pWb35Reg->EP0VM_spin_lock );
reg_queue = pWb35Reg->reg_first;
if (reg_queue == pWb35Reg->reg_last)
pWb35Reg->reg_last = NULL;
pWb35Reg->reg_first = pWb35Reg->reg_first->Next;
spin_unlock_irq( &pWb35Reg->EP0VM_spin_lock );
spin_lock_irq( &reg->EP0VM_spin_lock );
reg_queue = reg->reg_first;
if (reg_queue == reg->reg_last)
reg->reg_last = NULL;
reg->reg_first = reg->reg_first->Next;
spin_unlock_irq( &reg->EP0VM_spin_lock );
if (pWb35Reg->EP0VM_status) {
if (reg->EP0VM_status) {
#ifdef _PE_REG_DUMP_
WBDEBUG(("EP0 IoCompleteRoutine return error\n"));
DebugUsbdStatusInformation( pWb35Reg->EP0VM_status );
DebugUsbdStatusInformation( reg->EP0VM_status );
#endif
pWb35Reg->EP0vm_state = VM_STOP;
reg->EP0vm_state = VM_STOP;
pHwData->SurpriseRemove = 1;
} else {
// Success. Update the result
@ -499,7 +499,7 @@ Wb35Reg_EP0VM_complete(struct urb *urb)
void
Wb35Reg_destroy(phw_data_t pHwData)
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
struct urb *urb;
struct wb35_reg_queue *reg_queue;
@ -509,19 +509,19 @@ Wb35Reg_destroy(phw_data_t pHwData)
// Wait for Reg operation completed
do {
msleep(10); // Delay for waiting function enter 940623.1.a
} while (pWb35Reg->EP0vm_state != VM_STOP);
} while (reg->EP0vm_state != VM_STOP);
msleep(10); // Delay for waiting function enter 940623.1.b
// Release all the data in RegQueue
spin_lock_irq( &pWb35Reg->EP0VM_spin_lock );
reg_queue = pWb35Reg->reg_first;
spin_lock_irq(&reg->EP0VM_spin_lock);
reg_queue = reg->reg_first;
while (reg_queue) {
if (reg_queue == pWb35Reg->reg_last)
pWb35Reg->reg_last = NULL;
pWb35Reg->reg_first = pWb35Reg->reg_first->Next;
if (reg_queue == reg->reg_last)
reg->reg_last = NULL;
reg->reg_first = reg->reg_first->Next;
urb = reg_queue->urb;
spin_unlock_irq( &pWb35Reg->EP0VM_spin_lock );
spin_unlock_irq(&reg->EP0VM_spin_lock);
if (urb) {
usb_free_urb(urb);
kfree(reg_queue);
@ -530,11 +530,11 @@ Wb35Reg_destroy(phw_data_t pHwData)
WBDEBUG(("EP0 queue release error\n"));
#endif
}
spin_lock_irq( &pWb35Reg->EP0VM_spin_lock );
spin_lock_irq( &reg->EP0VM_spin_lock );
reg_queue = pWb35Reg->reg_first;
reg_queue = reg->reg_first;
}
spin_unlock_irq( &pWb35Reg->EP0VM_spin_lock );
spin_unlock_irq( &reg->EP0VM_spin_lock );
}
//====================================================================================
@ -542,35 +542,35 @@ Wb35Reg_destroy(phw_data_t pHwData)
//====================================================================================
unsigned char Wb35Reg_initial(phw_data_t pHwData)
{
PWB35REG pWb35Reg=&pHwData->Wb35Reg;
struct wb35_reg *reg=&pHwData->reg;
u32 ltmp;
u32 SoftwareSet, VCO_trim, TxVga, Region_ScanInterval;
// Spin lock is acquired for read and write IRP command
spin_lock_init( &pWb35Reg->EP0VM_spin_lock );
spin_lock_init( &reg->EP0VM_spin_lock );
// Getting RF module type from EEPROM ------------------------------------
Wb35Reg_WriteSync( pHwData, 0x03b4, 0x080d0000 ); // Start EEPROM access + Read + address(0x0d)
Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
//Update RF module type and determine the PHY type by inf or EEPROM
pWb35Reg->EEPROMPhyType = (u8)( ltmp & 0xff );
reg->EEPROMPhyType = (u8)( ltmp & 0xff );
// 0 V MAX2825, 1 V MAX2827, 2 V MAX2828, 3 V MAX2829
// 16V AL2230, 17 - AL7230, 18 - AL2230S
// 32 Reserved
// 33 - W89RF242(TxVGA 0~19), 34 - W89RF242(TxVGA 0~34)
if (pWb35Reg->EEPROMPhyType != RF_DECIDE_BY_INF) {
if( (pWb35Reg->EEPROMPhyType == RF_MAXIM_2825) ||
(pWb35Reg->EEPROMPhyType == RF_MAXIM_2827) ||
(pWb35Reg->EEPROMPhyType == RF_MAXIM_2828) ||
(pWb35Reg->EEPROMPhyType == RF_MAXIM_2829) ||
(pWb35Reg->EEPROMPhyType == RF_MAXIM_V1) ||
(pWb35Reg->EEPROMPhyType == RF_AIROHA_2230) ||
(pWb35Reg->EEPROMPhyType == RF_AIROHA_2230S) ||
(pWb35Reg->EEPROMPhyType == RF_AIROHA_7230) ||
(pWb35Reg->EEPROMPhyType == RF_WB_242) ||
(pWb35Reg->EEPROMPhyType == RF_WB_242_1))
pHwData->phy_type = pWb35Reg->EEPROMPhyType;
if (reg->EEPROMPhyType != RF_DECIDE_BY_INF) {
if( (reg->EEPROMPhyType == RF_MAXIM_2825) ||
(reg->EEPROMPhyType == RF_MAXIM_2827) ||
(reg->EEPROMPhyType == RF_MAXIM_2828) ||
(reg->EEPROMPhyType == RF_MAXIM_2829) ||
(reg->EEPROMPhyType == RF_MAXIM_V1) ||
(reg->EEPROMPhyType == RF_AIROHA_2230) ||
(reg->EEPROMPhyType == RF_AIROHA_2230S) ||
(reg->EEPROMPhyType == RF_AIROHA_7230) ||
(reg->EEPROMPhyType == RF_WB_242) ||
(reg->EEPROMPhyType == RF_WB_242_1))
pHwData->phy_type = reg->EEPROMPhyType;
}
// Power On procedure running. The relative parameter will be set according to phy_type
@ -606,9 +606,9 @@ unsigned char Wb35Reg_initial(phw_data_t pHwData)
if (pHwData->VCO_trim == 0xff)
pHwData->VCO_trim = 0x28;
pWb35Reg->EEPROMRegion = (u8)(Region_ScanInterval>>8); // 20060720
if( pWb35Reg->EEPROMRegion<1 || pWb35Reg->EEPROMRegion>6 )
pWb35Reg->EEPROMRegion = REGION_AUTO;
reg->EEPROMRegion = (u8)(Region_ScanInterval>>8); // 20060720
if( reg->EEPROMRegion<1 || reg->EEPROMRegion>6 )
reg->EEPROMRegion = REGION_AUTO;
//For Get Tx VGA from EEPROM 20060315.5 move here
GetTxVgaFromEEPROM( pHwData );

5
drivers/staging/winbond/linux/wb35reg_s.h
View File

@ -85,8 +85,7 @@ struct wb35_reg_queue {
// Internal variable for module
//====================================
#define MAX_SQ3_FILTER_SIZE 5
typedef struct _WB35REG
{
struct wb35_reg {
//============================
// Register Bank backup
//============================
@ -161,6 +160,6 @@ typedef struct _WB35REG
u32 SQ3_filter[MAX_SQ3_FILTER_SIZE];
u32 SQ3_index;
} WB35REG, *PWB35REG;
};

282
drivers/staging/winbond/reg.c
View File

@ -1191,10 +1191,10 @@ RFSynthesizer_initial(phw_data_t pHwData)
ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20);
Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
ltmp = pHwData->Wb35Reg.BB5C & 0xfffff000;
ltmp = pHwData->reg.BB5C & 0xfffff000;
Wb35Reg_WriteSync( pHwData, 0x105c, ltmp );
pHwData->Wb35Reg.BB50 |= 0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060315.1 modify
Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
pHwData->reg.BB50 |= 0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060315.1 modify
Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
msleep(5);
//phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01B0); //Activate Filter Cal.
@ -1212,9 +1212,9 @@ RFSynthesizer_initial(phw_data_t pHwData)
Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
// //Force TXI(Q)P(N) to normal control
Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->Wb35Reg.BB5C );
pHwData->Wb35Reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);
Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->reg.BB5C );
pHwData->reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);
Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->reg.BB50);
break;
case RF_AIROHA_7230:
@ -1280,11 +1280,11 @@ RFSynthesizer_initial(phw_data_t pHwData)
//
// ; Version 1.3B revision items: for FA5976A , October 3, 2005 by HTHo
//
ltmp = pHwData->Wb35Reg.BB5C & 0xfffff000;
ltmp = pHwData->reg.BB5C & 0xfffff000;
Wb35Reg_WriteSync( pHwData, 0x105c, ltmp );
Wb35Reg_WriteSync( pHwData, 0x1058, 0 );
pHwData->Wb35Reg.BB50 |= 0x3;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060630
Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
pHwData->reg.BB50 |= 0x3;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060630
Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
//----- Calibration (1). VCO frequency calibration
//Calibration (1a.0). Synthesizer reset (HTHo corrected 2005/05/10)
@ -1405,9 +1405,9 @@ RFSynthesizer_initial(phw_data_t pHwData)
msleep(5); // Sleep 5 ms
// //write back
// Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->Wb35Reg.BB5C );
// pHwData->Wb35Reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START); // 20060315.1 fix
// Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
// Wb35Reg_WriteSync(pHwData, 0x105c, pHwData->reg.BB5C);
// pHwData->reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START); // 20060315.1 fix
// Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
// msleep(1); // Sleep 1 ms
break;
}
@ -1415,14 +1415,14 @@ RFSynthesizer_initial(phw_data_t pHwData)
void BBProcessor_AL7230_2400( phw_data_t pHwData)
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
u32 pltmp[12];
pltmp[0] = 0x16A8337A; // 0x16a5215f; // 0x1000 AGC_Ctrl1
pltmp[1] = 0x9AFF9AA6; // 0x9aff9ca6; // 0x1004 AGC_Ctrl2
pltmp[2] = 0x55D00A04; // 0x55d00a04; // 0x1008 AGC_Ctrl3
pltmp[3] = 0xFFF72031; // 0xFfFf2138; // 0x100c AGC_Ctrl4
pWb35Reg->BB0C = 0xFFF72031;
reg->BB0C = 0xFFF72031;
pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7
pltmp[5] = 0x00CAA333; // 0x00eaa333; // 0x1014 AGC_Ctrl6
pltmp[6] = 0xF2211111; // 0x11111111; // 0x1018 AGC_Ctrl7
@ -1431,25 +1431,25 @@ void BBProcessor_AL7230_2400( phw_data_t pHwData)
pltmp[9] = 0xA8002A79; // 0xa9002A79; // 0x1024 AGC_Ctrl10
pltmp[10] = 0x40000528; // 20050927 0x40000228
pltmp[11] = 0x232D7F30; // 0x23457f30;// 0x102c A_ACQ_Ctrl
pWb35Reg->BB2C = 0x232D7F30;
reg->BB2C = 0x232D7F30;
Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
pltmp[0] = 0x00002c54; // 0x1030 B_ACQ_Ctrl
pWb35Reg->BB30 = 0x00002c54;
reg->BB30 = 0x00002c54;
pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
pWb35Reg->BB3C = 0x00000000;
reg->BB3C = 0x00000000;
pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
pltmp[6] = 0x00332C1B; // 0x00453B24; // 0x1048 11b TX RC filter
pltmp[7] = 0x0A00FEFF; // 0x0E00FEFF; // 0x104c 11b TX RC filter
pltmp[8] = 0x2B106208; // 0x1050 MODE_Ctrl
pWb35Reg->BB50 = 0x2B106208;
reg->BB50 = 0x2B106208;
pltmp[9] = 0; // 0x1054
pWb35Reg->BB54 = 0x00000000;
reg->BB54 = 0x00000000;
pltmp[10] = 0x52524242; // 0x64645252; // 0x1058 IQ_Alpha
pWb35Reg->BB58 = 0x52524242;
reg->BB58 = 0x52524242;
pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
@ -1457,14 +1457,14 @@ void BBProcessor_AL7230_2400( phw_data_t pHwData)
void BBProcessor_AL7230_5000( phw_data_t pHwData)
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
u32 pltmp[12];
pltmp[0] = 0x16AA6678; // 0x1000 AGC_Ctrl1
pltmp[1] = 0x9AFFA0B2; // 0x1004 AGC_Ctrl2
pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
pltmp[3] = 0xEFFF233E; // 0x100c AGC_Ctrl4
pWb35Reg->BB0C = 0xEFFF233E;
reg->BB0C = 0xEFFF233E;
pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7
pltmp[5] = 0x00CAA333; // 0x1014 AGC_Ctrl6
pltmp[6] = 0xF2432111; // 0x1018 AGC_Ctrl7
@ -1473,24 +1473,24 @@ void BBProcessor_AL7230_5000( phw_data_t pHwData)
pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
pltmp[10] = 0x40000528; // 20050927 0x40000228
pltmp[11] = 0x232FDF30;// 0x102c A_ACQ_Ctrl
pWb35Reg->BB2C = 0x232FDF30;
reg->BB2C = 0x232FDF30;
Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
pltmp[0] = 0x80002C7C; // 0x1030 B_ACQ_Ctrl
pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
pWb35Reg->BB3C = 0x00000000;
reg->BB3C = 0x00000000;
pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
pltmp[6] = 0x00332C1B; // 0x1048 11b TX RC filter
pltmp[7] = 0x0A00FEFF; // 0x104c 11b TX RC filter
pltmp[8] = 0x2B107208; // 0x1050 MODE_Ctrl
pWb35Reg->BB50 = 0x2B107208;
reg->BB50 = 0x2B107208;
pltmp[9] = 0; // 0x1054
pWb35Reg->BB54 = 0x00000000;
reg->BB54 = 0x00000000;
pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha
pWb35Reg->BB58 = 0x52524242;
reg->BB58 = 0x52524242;
pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
@ -1511,7 +1511,7 @@ void BBProcessor_AL7230_5000( phw_data_t pHwData)
void
BBProcessor_initial( phw_data_t pHwData )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
u32 i, pltmp[12];
switch( pHwData->phy_type )
@ -1522,7 +1522,7 @@ BBProcessor_initial( phw_data_t pHwData )
pltmp[1] = 0x9AFFAEA4; // 0x1004 AGC_Ctrl2
pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
pltmp[3] = 0xEFFF1A34; // 0x100c AGC_Ctrl4
pWb35Reg->BB0C = 0xEFFF1A34;
reg->BB0C = 0xEFFF1A34;
pltmp[4] = 0x0FABE0B7; // 0x1010 AGC_Ctrl5
pltmp[5] = 0x00CAA332; // 0x1014 AGC_Ctrl6
pltmp[6] = 0xF6632111; // 0x1018 AGC_Ctrl7
@ -1531,25 +1531,25 @@ BBProcessor_initial( phw_data_t pHwData )
pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
pltmp[10] = (pHwData->phy_type==3) ? 0x40000a28 : 0x40000228; // 0x1028 MAXIM_331(b31=0) + WBRF_V1(b11=1) : MAXIM_331(b31=0) + WBRF_V2(b11=0)
pltmp[11] = 0x232FDF30; // 0x102c A_ACQ_Ctrl
pWb35Reg->BB2C = 0x232FDF30; //Modify for 33's 1.0.95.xxx version, antenna 1
reg->BB2C = 0x232FDF30; //Modify for 33's 1.0.95.xxx version, antenna 1
Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
pWb35Reg->BB30 = 0x00002C54;
reg->BB30 = 0x00002C54;
pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl
pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
pWb35Reg->BB3C = 0x00000000;
reg->BB3C = 0x00000000;
pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter
pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
pWb35Reg->BB50 = 0x27106208;
reg->BB50 = 0x27106208;
pltmp[9] = 0; // 0x1054
pWb35Reg->BB54 = 0x00000000;
reg->BB54 = 0x00000000;
pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha
pWb35Reg->BB58 = 0x64646464;
reg->BB58 = 0x64646464;
pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
@ -1568,7 +1568,7 @@ BBProcessor_initial( phw_data_t pHwData )
pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2
pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
pltmp[3] = 0xefff1a34; // 0x100c AGC_Ctrl4
pWb35Reg->BB0C = 0xefff1a34;
reg->BB0C = 0xefff1a34;
pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5
pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6
pltmp[6] = 0xf6632111; // 0x1018 AGC_Ctrl7
@ -1577,25 +1577,25 @@ BBProcessor_initial( phw_data_t pHwData )
pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
pltmp[10] = 0x40000528; // 0x40000128; Modify for 33's 1.0.95
pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl
pWb35Reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1
reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1
Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
pWb35Reg->BB30 = 0x00002C54;
reg->BB30 = 0x00002C54;
pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl
pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
pWb35Reg->BB3C = 0x00000000;
reg->BB3C = 0x00000000;
pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
pltmp[7] = 0x0D00FDFF; // 0x104c 11b TX RC filter
pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
pWb35Reg->BB50 = 0x27106208;
reg->BB50 = 0x27106208;
pltmp[9] = 0; // 0x1054
pWb35Reg->BB54 = 0x00000000;
reg->BB54 = 0x00000000;
pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha
pWb35Reg->BB58 = 0x64646464;
reg->BB58 = 0x64646464;
pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel
Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
@ -1608,7 +1608,7 @@ BBProcessor_initial( phw_data_t pHwData )
pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2
pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
pltmp[3] = 0xf4ff1632; // 0xefff1a34; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95
pWb35Reg->BB0C = 0xf4ff1632; // 0xefff1a34; Modify for 33's 1.0.95
reg->BB0C = 0xf4ff1632; // 0xefff1a34; Modify for 33's 1.0.95
pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5
pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6
pltmp[6] = 0xf8632112; // 0xf6632111; // 0x1018 AGC_Ctrl7 Modify for 33's 1.0.95
@ -1617,25 +1617,25 @@ BBProcessor_initial( phw_data_t pHwData )
pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
pltmp[10] = 0x40000528; // 0x40000128; modify for 33's 1.0.95
pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl
pWb35Reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1
reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1
Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
pWb35Reg->BB30 = 0x00002C54;
reg->BB30 = 0x00002C54;
pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
pltmp[2] = 0x5b2c8769; // 0x5B6C8769; // 0x1038 B_TXRX_Ctrl Modify for 33's 1.0.95
pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
pWb35Reg->BB3C = 0x00000000;
reg->BB3C = 0x00000000;
pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
pltmp[6] = 0x002c2617; // 0x00453B24; // 0x1048 11b TX RC filter Modify for 33's 1.0.95
pltmp[7] = 0x0800feff; // 0x0D00FDFF; // 0x104c 11b TX RC filter Modify for 33's 1.0.95
pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
pWb35Reg->BB50 = 0x27106208;
reg->BB50 = 0x27106208;
pltmp[9] = 0; // 0x1054
pWb35Reg->BB54 = 0x00000000;
reg->BB54 = 0x00000000;
pltmp[10] = 0x64644a4a; // 0x64646464; // 0x1058 IQ_Alpha Modify for 33's 1.0.95
pWb35Reg->BB58 = 0x64646464;
reg->BB58 = 0x64646464;
pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel
Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
@ -1648,7 +1648,7 @@ BBProcessor_initial( phw_data_t pHwData )
pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version
pWb35Reg->BB0C = 0xFFFd203c;
reg->BB0C = 0xFFFd203c;
pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version
pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version
pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version
@ -1657,27 +1657,27 @@ BBProcessor_initial( phw_data_t pHwData )
pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
pltmp[10] = 0X40000528; //0x40000228
pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730
pWb35Reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1
reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1
Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
pWb35Reg->BB30 = 0x00002C54;
reg->BB30 = 0x00002C54;
pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769
pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
pWb35Reg->BB3C = 0x00000000;
reg->BB3C = 0x00000000;
pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2
pWb35Reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2
reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2
pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2
pWb35Reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1 20060613.2
reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1 20060613.2
pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
pWb35Reg->BB50 = 0x27106200;
reg->BB50 = 0x27106200;
pltmp[9] = 0; // 0x1054
pWb35Reg->BB54 = 0x00000000;
reg->BB54 = 0x00000000;
pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha
pWb35Reg->BB58 = 0x52524242;
reg->BB58 = 0x52524242;
pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
@ -1690,7 +1690,7 @@ BBProcessor_initial( phw_data_t pHwData )
pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version
pWb35Reg->BB0C = 0xFFFd203c;
reg->BB0C = 0xFFFd203c;
pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version
pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version
pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version
@ -1699,27 +1699,27 @@ BBProcessor_initial( phw_data_t pHwData )
pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
pltmp[10] = 0X40000528; //0x40000228
pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730
pWb35Reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1
reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1
Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
pWb35Reg->BB30 = 0x00002C54;
reg->BB30 = 0x00002C54;
pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769
pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
pWb35Reg->BB3C = 0x00000000;
reg->BB3C = 0x00000000;
pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2
pWb35Reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2
reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2
pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2
pWb35Reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1
reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1
pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
pWb35Reg->BB50 = 0x27106200;
reg->BB50 = 0x27106200;
pltmp[9] = 0; // 0x1054
pWb35Reg->BB54 = 0x00000000;
reg->BB54 = 0x00000000;
pltmp[10] = 0x52523232; // 20060419 0x52524242; // 0x1058 IQ_Alpha
pWb35Reg->BB58 = 0x52523232; // 20060419 0x52524242;
reg->BB58 = 0x52523232; // 20060419 0x52524242;
pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
@ -1732,7 +1732,7 @@ BBProcessor_initial( phw_data_t pHwData )
pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
pltmp[3] = 0xFFFb203a; // 0x100c AGC_Ctrl4
pWb35Reg->BB0c = 0xFFFb203a;
reg->BB0c = 0xFFFb203a;
pltmp[4] = 0x0FBFDCB7; // 0x1010 AGC_Ctrl5
pltmp[5] = 0x00caa333; // 0x1014 AGC_Ctrl6
pltmp[6] = 0xf6632112; // 0x1018 AGC_Ctrl7
@ -1741,25 +1741,25 @@ BBProcessor_initial( phw_data_t pHwData )
pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
pltmp[10] = 0x40000228;
pltmp[11] = 0x232A9F30;// 0x102c A_ACQ_Ctrl
pWb35Reg->BB2c = 0x232A9F30;
reg->BB2c = 0x232A9F30;
Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
pWb35Reg->BB30 = 0x00002C54;
reg->BB30 = 0x00002C54;
pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
pWb35Reg->BB3c = 0x00000000;
reg->BB3c = 0x00000000;
pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter
pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
pWb35Reg->BB50 = 0x27106200;
reg->BB50 = 0x27106200;
pltmp[9] = 0; // 0x1054
pWb35Reg->BB54 = 0x00000000;
reg->BB54 = 0x00000000;
pltmp[10] = 0x64645252; // 0x1058 IQ_Alpha
pWb35Reg->BB58 = 0x64645252;
reg->BB58 = 0x64645252;
pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
*/
@ -1775,7 +1775,7 @@ BBProcessor_initial( phw_data_t pHwData )
pltmp[1] = 0x9AFF9ABA; // 0x1004 AGC_Ctrl2
pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
pltmp[3] = 0xEEE91C32; // 0x100c AGC_Ctrl4
pWb35Reg->BB0C = 0xEEE91C32;
reg->BB0C = 0xEEE91C32;
pltmp[4] = 0x0FACDCC5; // 0x1010 AGC_Ctrl5
pltmp[5] = 0x000AA344; // 0x1014 AGC_Ctrl6
pltmp[6] = 0x22222221; // 0x1018 AGC_Ctrl7
@ -1784,27 +1784,27 @@ BBProcessor_initial( phw_data_t pHwData )
pltmp[9] = 0xA9002A79; // 0x1024 AGC_Ctrl10
pltmp[10] = 0x40000528; // 0x1028
pltmp[11] = 0x23457F30; // 0x102c A_ACQ_Ctrl
pWb35Reg->BB2C = 0x23457F30;
reg->BB2C = 0x23457F30;
Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
pWb35Reg->BB30 = 0x00002C54;
reg->BB30 = 0x00002C54;
pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
pltmp[3] = pHwData->BB3c_cal; // 0x103c 11a TX LS filter
pWb35Reg->BB3C = pHwData->BB3c_cal;
reg->BB3C = pHwData->BB3c_cal;
pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
pltmp[6] = BB48_DEFAULT_WB242_11G; // 0x1048 11b TX RC filter 20060613.2
pWb35Reg->BB48 = BB48_DEFAULT_WB242_11G; // 20060613.1 20060613.2
reg->BB48 = BB48_DEFAULT_WB242_11G; // 20060613.1 20060613.2
pltmp[7] = BB4C_DEFAULT_WB242_11G; // 0x104c 11b TX RC filter 20060613.2
pWb35Reg->BB4C = BB4C_DEFAULT_WB242_11G; // 20060613.1 20060613.2
reg->BB4C = BB4C_DEFAULT_WB242_11G; // 20060613.1 20060613.2
pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
pWb35Reg->BB50 = 0x27106208;
reg->BB50 = 0x27106208;
pltmp[9] = pHwData->BB54_cal; // 0x1054
pWb35Reg->BB54 = pHwData->BB54_cal;
reg->BB54 = pHwData->BB54_cal;
pltmp[10] = 0x52523131; // 0x1058 IQ_Alpha
pWb35Reg->BB58 = 0x52523131;
reg->BB58 = 0x52523131;
pltmp[11] = 0xAA0AC000; // 20060825 0xAA2AC000; // 0x105c DC_Cancel
Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
@ -1813,14 +1813,14 @@ BBProcessor_initial( phw_data_t pHwData )
}
// Fill the LNA table
pWb35Reg->LNAValue[0] = (u8)(pWb35Reg->BB0C & 0xff);
pWb35Reg->LNAValue[1] = 0;
pWb35Reg->LNAValue[2] = (u8)((pWb35Reg->BB0C & 0xff00)>>8);
pWb35Reg->LNAValue[3] = 0;
reg->LNAValue[0] = (u8)(reg->BB0C & 0xff);
reg->LNAValue[1] = 0;
reg->LNAValue[2] = (u8)((reg->BB0C & 0xff00)>>8);
reg->LNAValue[3] = 0;
// Fill SQ3 table
for( i=0; i<MAX_SQ3_FILTER_SIZE; i++ )
pWb35Reg->SQ3_filter[i] = 0x2f; // half of Bit 0 ~ 6
reg->SQ3_filter[i] = 0x2f; // half of Bit 0 ~ 6
}
void set_tx_power_per_channel_max2829( phw_data_t pHwData, ChanInfo Channel)
@ -1903,7 +1903,7 @@ void set_tx_power_per_channel_wb242( phw_data_t pHwData, ChanInfo Channel)
void
RFSynthesizer_SwitchingChannel( phw_data_t pHwData, ChanInfo Channel )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
u32 pltmp[16]; // The 16 is the maximum capability of hardware
u32 count, ltmp;
u8 i, j, number;
@ -2090,40 +2090,40 @@ RFSynthesizer_SwitchingChannel( phw_data_t pHwData, ChanInfo Channel )
if( Channel.band <= BAND_TYPE_OFDM_24 )
{
// BB: select 2.4 GHz, bit[12-11]=00
pWb35Reg->BB50 &= ~(BIT(11)|BIT(12));
Wb35Reg_Write( pHwData, 0x1050, pWb35Reg->BB50 ); // MODE_Ctrl
reg->BB50 &= ~(BIT(11)|BIT(12));
Wb35Reg_Write( pHwData, 0x1050, reg->BB50 ); // MODE_Ctrl
// MAC: select 2.4 GHz, bit[5]=0
pWb35Reg->M78_ERPInformation &= ~BIT(5);
Wb35Reg_Write( pHwData, 0x0878, pWb35Reg->M78_ERPInformation );
reg->M78_ERPInformation &= ~BIT(5);
Wb35Reg_Write( pHwData, 0x0878, reg->M78_ERPInformation );
// enable 11b Baseband
pWb35Reg->BB30 &= ~BIT(31);
Wb35Reg_Write( pHwData, 0x1030, pWb35Reg->BB30 );
reg->BB30 &= ~BIT(31);
Wb35Reg_Write( pHwData, 0x1030, reg->BB30 );
}
else if( (Channel.band == BAND_TYPE_OFDM_5) )
{
// BB: select 5 GHz
pWb35Reg->BB50 &= ~(BIT(11)|BIT(12));
reg->BB50 &= ~(BIT(11)|BIT(12));
if (Channel.ChanNo <=64 )
pWb35Reg->BB50 |= BIT(12); // 10-5.25GHz
reg->BB50 |= BIT(12); // 10-5.25GHz
else if ((Channel.ChanNo >= 100) && (Channel.ChanNo <= 124))
pWb35Reg->BB50 |= BIT(11); // 01-5.48GHz
reg->BB50 |= BIT(11); // 01-5.48GHz
else if ((Channel.ChanNo >=128) && (Channel.ChanNo <= 161))
pWb35Reg->BB50 |= (BIT(12)|BIT(11)); // 11-5.775GHz
reg->BB50 |= (BIT(12)|BIT(11)); // 11-5.775GHz
else //Chan 184 ~ 196 will use bit[12-11] = 10 in version sh-src-1.2.25
pWb35Reg->BB50 |= BIT(12);
Wb35Reg_Write( pHwData, 0x1050, pWb35Reg->BB50 ); // MODE_Ctrl
reg->BB50 |= BIT(12);
Wb35Reg_Write( pHwData, 0x1050, reg->BB50 ); // MODE_Ctrl
//(1) M78 should alway use 2.4G setting when using RF_AIROHA_7230
//(2) BB30 has been updated previously.
if (pHwData->phy_type != RF_AIROHA_7230)
{
// MAC: select 5 GHz, bit[5]=1
pWb35Reg->M78_ERPInformation |= BIT(5);
Wb35Reg_Write( pHwData, 0x0878, pWb35Reg->M78_ERPInformation );
reg->M78_ERPInformation |= BIT(5);
Wb35Reg_Write( pHwData, 0x0878, reg->M78_ERPInformation );
// disable 11b Baseband
pWb35Reg->BB30 |= BIT(31);
Wb35Reg_Write( pHwData, 0x1030, pWb35Reg->BB30 );
reg->BB30 |= BIT(31);
Wb35Reg_Write( pHwData, 0x1030, reg->BB30 );
}
}
}
@ -2313,21 +2313,21 @@ u8 RFSynthesizer_SetWinbond242Power( phw_data_t pHwData, u8 index )
//===========================================================================================================
void Dxx_initial( phw_data_t pHwData )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
// Old IC:Single mode only.
// New IC: operation decide by Software set bit[4]. 1:multiple 0: single
pWb35Reg->D00_DmaControl = 0xc0000004; //Txon, Rxon, multiple Rx for new 4k DMA
reg->D00_DmaControl = 0xc0000004; //Txon, Rxon, multiple Rx for new 4k DMA
//Txon, Rxon, single Rx for old 8k ASIC
if( !HAL_USB_MODE_BURST( pHwData ) )
pWb35Reg->D00_DmaControl = 0xc0000000;//Txon, Rxon, single Rx for new 4k DMA
reg->D00_DmaControl = 0xc0000000;//Txon, Rxon, single Rx for new 4k DMA
Wb35Reg_WriteSync( pHwData, 0x0400, pWb35Reg->D00_DmaControl );
Wb35Reg_WriteSync( pHwData, 0x0400, reg->D00_DmaControl );
}
void Mxx_initial( phw_data_t pHwData )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
u32 tmp;
u32 pltmp[11];
u16 i;
@ -2339,23 +2339,23 @@ void Mxx_initial( phw_data_t pHwData )
// M00 bit set
#ifdef _IBSS_BEACON_SEQ_STICK_
pWb35Reg->M00_MacControl = 0; // Solve beacon sequence number stop by software
reg->M00_MacControl = 0; // Solve beacon sequence number stop by software
#else
pWb35Reg->M00_MacControl = 0x80000000; // Solve beacon sequence number stop by hardware
reg->M00_MacControl = 0x80000000; // Solve beacon sequence number stop by hardware
#endif
// M24 disable enter power save, BB RxOn and enable NAV attack
pWb35Reg->M24_MacControl = 0x08040042;
pltmp[0] = pWb35Reg->M24_MacControl;
reg->M24_MacControl = 0x08040042;
pltmp[0] = reg->M24_MacControl;
pltmp[1] = 0; // Skip M28, because no initialize value is required.
// M2C CWmin and CWmax setting
pHwData->cwmin = DEFAULT_CWMIN;
pHwData->cwmax = DEFAULT_CWMAX;
pWb35Reg->M2C_MacControl = DEFAULT_CWMIN << 10;
pWb35Reg->M2C_MacControl |= DEFAULT_CWMAX;
pltmp[2] = pWb35Reg->M2C_MacControl;
reg->M2C_MacControl = DEFAULT_CWMIN << 10;
reg->M2C_MacControl |= DEFAULT_CWMAX;
pltmp[2] = reg->M2C_MacControl;
// M30 BSSID
pltmp[3] = *(u32 *)pHwData->bssid;
@ -2367,35 +2367,35 @@ void Mxx_initial( phw_data_t pHwData )
pltmp[4] = tmp;
// M38
pWb35Reg->M38_MacControl = (DEFAULT_RATE_RETRY_LIMIT<<8) | (DEFAULT_LONG_RETRY_LIMIT << 4) | DEFAULT_SHORT_RETRY_LIMIT;
pltmp[5] = pWb35Reg->M38_MacControl;
reg->M38_MacControl = (DEFAULT_RATE_RETRY_LIMIT<<8) | (DEFAULT_LONG_RETRY_LIMIT << 4) | DEFAULT_SHORT_RETRY_LIMIT;
pltmp[5] = reg->M38_MacControl;
// M3C
tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST ;
pWb35Reg->M3C_MacControl = tmp;
reg->M3C_MacControl = tmp;
pltmp[6] = tmp;
// M40
pHwData->slot_time_select = DEFAULT_SLOT_TIME;
tmp = (DEFAULT_ATIMWD << 16) | DEFAULT_SLOT_TIME;
pWb35Reg->M40_MacControl = tmp;
reg->M40_MacControl = tmp;
pltmp[7] = tmp;
// M44
tmp = DEFAULT_MAX_TX_MSDU_LIFE_TIME << 10; // *1024
pWb35Reg->M44_MacControl = tmp;
reg->M44_MacControl = tmp;
pltmp[8] = tmp;
// M48
pHwData->BeaconPeriod = DEFAULT_BEACON_INTERVAL;
pHwData->ProbeDelay = DEFAULT_PROBE_DELAY_TIME;
tmp = (DEFAULT_BEACON_INTERVAL << 16) | DEFAULT_PROBE_DELAY_TIME;
pWb35Reg->M48_MacControl = tmp;
reg->M48_MacControl = tmp;
pltmp[9] = tmp;
//M4C
pWb35Reg->M4C_MacStatus = (DEFAULT_PROTOCOL_VERSION << 30) | (DEFAULT_MAC_POWER_STATE << 28) | (DEFAULT_DTIM_ALERT_TIME << 24);
pltmp[10] = pWb35Reg->M4C_MacStatus;
reg->M4C_MacStatus = (DEFAULT_PROTOCOL_VERSION << 30) | (DEFAULT_MAC_POWER_STATE << 28) | (DEFAULT_DTIM_ALERT_TIME << 24);
pltmp[10] = reg->M4C_MacStatus;
// Burst write
//Wb35Reg_BurstWrite( pHwData, 0x0824, pltmp, 11, AUTO_INCREMENT );
@ -2404,15 +2404,15 @@ void Mxx_initial( phw_data_t pHwData )
// M60
Wb35Reg_WriteSync( pHwData, 0x0860, 0x12481248 );
pWb35Reg->M60_MacControl = 0x12481248;
reg->M60_MacControl = 0x12481248;
// M68
Wb35Reg_WriteSync( pHwData, 0x0868, 0x00050900 ); // 20051018 0x000F0F00 ); // 940930 0x00131300
pWb35Reg->M68_MacControl = 0x00050900;
reg->M68_MacControl = 0x00050900;
// M98
Wb35Reg_WriteSync( pHwData, 0x0898, 0xffff8888 );
pWb35Reg->M98_MacControl = 0xffff8888;
reg->M98_MacControl = 0xffff8888;
}
@ -2620,7 +2620,7 @@ void EEPROMTxVgaAdjust( phw_data_t pHwData ) // 20060619.5 Add
void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ) // 20060613.1
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
unsigned char Is11bRate;
Is11bRate = (rate % 6) ? 1 : 0;
@ -2630,8 +2630,8 @@ void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ) // 20060613.1
case RF_AIROHA_2230S: // 20060420 Add this
if( Is11bRate )
{
if( (pWb35Reg->BB48 != BB48_DEFAULT_AL2230_11B) &&
(pWb35Reg->BB4C != BB4C_DEFAULT_AL2230_11B) )
if( (reg->BB48 != BB48_DEFAULT_AL2230_11B) &&
(reg->BB4C != BB4C_DEFAULT_AL2230_11B) )
{
Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11B );
Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11B );
@ -2639,8 +2639,8 @@ void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ) // 20060613.1
}
else
{
if( (pWb35Reg->BB48 != BB48_DEFAULT_AL2230_11G) &&
(pWb35Reg->BB4C != BB4C_DEFAULT_AL2230_11G) )
if( (reg->BB48 != BB48_DEFAULT_AL2230_11G) &&
(reg->BB4C != BB4C_DEFAULT_AL2230_11G) )
{
Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11G );
Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11G );
@ -2651,22 +2651,22 @@ void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ) // 20060613.1
case RF_WB_242: // 20060623 The fix only for old TxVGA setting
if( Is11bRate )
{
if( (pWb35Reg->BB48 != BB48_DEFAULT_WB242_11B) &&
(pWb35Reg->BB4C != BB4C_DEFAULT_WB242_11B) )
if( (reg->BB48 != BB48_DEFAULT_WB242_11B) &&
(reg->BB4C != BB4C_DEFAULT_WB242_11B) )
{
pWb35Reg->BB48 = BB48_DEFAULT_WB242_11B;
pWb35Reg->BB4C = BB4C_DEFAULT_WB242_11B;
reg->BB48 = BB48_DEFAULT_WB242_11B;
reg->BB4C = BB4C_DEFAULT_WB242_11B;
Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11B );
Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11B );
}
}
else
{
if( (pWb35Reg->BB48 != BB48_DEFAULT_WB242_11G) &&
(pWb35Reg->BB4C != BB4C_DEFAULT_WB242_11G) )
if( (reg->BB48 != BB48_DEFAULT_WB242_11G) &&
(reg->BB4C != BB4C_DEFAULT_WB242_11G) )
{
pWb35Reg->BB48 = BB48_DEFAULT_WB242_11G;
pWb35Reg->BB4C = BB4C_DEFAULT_WB242_11G;
reg->BB48 = BB48_DEFAULT_WB242_11G;
reg->BB4C = BB4C_DEFAULT_WB242_11G;
Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11G );
Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11G );
}

260
drivers/staging/winbond/wbhal.c
View File

@ -92,7 +92,7 @@ void hal_halt(phw_data_t pHwData, void *ppa_data)
void hal_set_rates(phw_data_t pHwData, u8 *pbss_rates,
u8 length, unsigned char basic_rate_set)
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
u32 tmp, tmp1;
u8 Rate[12]={ 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 };
u8 SupportedRate[16];
@ -101,10 +101,10 @@ void hal_set_rates(phw_data_t pHwData, u8 *pbss_rates,
if( pHwData->SurpriseRemove ) return;
if (basic_rate_set) {
pWb35Reg->M28_MacControl &= ~0x000fff00;
reg->M28_MacControl &= ~0x000fff00;
tmp1 = 0x00000100;
} else {
pWb35Reg->M28_MacControl &= ~0xfff00000;
reg->M28_MacControl &= ~0xfff00000;
tmp1 = 0x00100000;
}
@ -120,8 +120,8 @@ void hal_set_rates(phw_data_t pHwData, u8 *pbss_rates,
tmp |= (tmp1<<j);
}
pWb35Reg->M28_MacControl |= tmp;
Wb35Reg_Write( pHwData, 0x0828, pWb35Reg->M28_MacControl );
reg->M28_MacControl |= tmp;
Wb35Reg_Write( pHwData, 0x0828, reg->M28_MacControl );
// 930206.2.c M78 setting
j = k = Count1 = Count2 = 0;
@ -129,10 +129,10 @@ void hal_set_rates(phw_data_t pHwData, u8 *pbss_rates,
tmp = 0x00100000;
tmp1 = 0x00000100;
for (i=0; i<12; i++) { // Get the supported rate
if (tmp & pWb35Reg->M28_MacControl) {
if (tmp & reg->M28_MacControl) {
SupportedRate[j] = Rate[i];
if (tmp1 & pWb35Reg->M28_MacControl)
if (tmp1 & reg->M28_MacControl)
SupportedRate[j] |= 0x80;
if (k)
@ -144,7 +144,7 @@ void hal_set_rates(phw_data_t pHwData, u8 *pbss_rates,
}
if (i==4 && k==0) {
if( !(pWb35Reg->M28_MacControl & 0x000ff000) ) // if basic rate in 11g domain)
if( !(reg->M28_MacControl & 0x000ff000) ) // if basic rate in 11g domain)
{
k = 1;
j = 8;
@ -161,16 +161,16 @@ void hal_set_rates(phw_data_t pHwData, u8 *pbss_rates,
*(u32 *)(SupportedRate+(i<<2)) = cpu_to_le32( *(u32 *)(SupportedRate+(i<<2)) );
//--- end 20060926 add by anson's endian
Wb35Reg_BurstWrite( pHwData,0x087c, (u32 *)SupportedRate, 4, AUTO_INCREMENT );
pWb35Reg->M7C_MacControl = ((u32 *)SupportedRate)[0];
pWb35Reg->M80_MacControl = ((u32 *)SupportedRate)[1];
pWb35Reg->M84_MacControl = ((u32 *)SupportedRate)[2];
pWb35Reg->M88_MacControl = ((u32 *)SupportedRate)[3];
reg->M7C_MacControl = ((u32 *)SupportedRate)[0];
reg->M80_MacControl = ((u32 *)SupportedRate)[1];
reg->M84_MacControl = ((u32 *)SupportedRate)[2];
reg->M88_MacControl = ((u32 *)SupportedRate)[3];
// Fill length
tmp = Count1<<28 | Count2<<24;
pWb35Reg->M78_ERPInformation &= ~0xff000000;
pWb35Reg->M78_ERPInformation |= tmp;
Wb35Reg_Write( pHwData, 0x0878, pWb35Reg->M78_ERPInformation );
reg->M78_ERPInformation &= ~0xff000000;
reg->M78_ERPInformation |= tmp;
Wb35Reg_Write( pHwData, 0x0878, reg->M78_ERPInformation );
}
@ -190,7 +190,7 @@ void hal_set_beacon_period( phw_data_t pHwData, u16 beacon_period )
void hal_set_current_channel_ex( phw_data_t pHwData, ChanInfo channel )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
if( pHwData->SurpriseRemove )
return;
@ -203,9 +203,9 @@ void hal_set_current_channel_ex( phw_data_t pHwData, ChanInfo channel )
#ifdef _PE_STATE_DUMP_
WBDEBUG(("Set channel is %d, band =%d\n", pHwData->Channel, pHwData->band));
#endif
pWb35Reg->M28_MacControl &= ~0xff; // Clean channel information field
pWb35Reg->M28_MacControl |= channel.ChanNo;
Wb35Reg_WriteWithCallbackValue( pHwData, 0x0828, pWb35Reg->M28_MacControl,
reg->M28_MacControl &= ~0xff; // Clean channel information field
reg->M28_MacControl |= channel.ChanNo;
Wb35Reg_WriteWithCallbackValue( pHwData, 0x0828, reg->M28_MacControl,
(s8 *)&channel, sizeof(ChanInfo));
}
//---------------------------------------------------------------------------------------------------
@ -222,47 +222,47 @@ void hal_get_current_channel( phw_data_t pHwData, ChanInfo *channel )
//---------------------------------------------------------------------------------------------------
void hal_set_accept_broadcast( phw_data_t pHwData, u8 enable )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
if( pHwData->SurpriseRemove ) return;
pWb35Reg->M00_MacControl &= ~0x02000000;//The HW value
reg->M00_MacControl &= ~0x02000000;//The HW value
if (enable)
pWb35Reg->M00_MacControl |= 0x02000000;//The HW value
reg->M00_MacControl |= 0x02000000;//The HW value
Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl );
}
//for wep key error detection, we need to accept broadcast packets to be received temporary.
void hal_set_accept_promiscuous( phw_data_t pHwData, u8 enable)
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
if (pHwData->SurpriseRemove) return;
if (enable) {
pWb35Reg->M00_MacControl |= 0x00400000;
Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
reg->M00_MacControl |= 0x00400000;
Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl );
} else {
pWb35Reg->M00_MacControl&=~0x00400000;
Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
reg->M00_MacControl&=~0x00400000;
Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl );
}
}
void hal_set_accept_multicast( phw_data_t pHwData, u8 enable )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
if( pHwData->SurpriseRemove ) return;
pWb35Reg->M00_MacControl &= ~0x01000000;//The HW value
if (enable) pWb35Reg->M00_MacControl |= 0x01000000;//The HW value
Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
reg->M00_MacControl &= ~0x01000000;//The HW value
if (enable) reg->M00_MacControl |= 0x01000000;//The HW value
Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl );
}
void hal_set_accept_beacon( phw_data_t pHwData, u8 enable )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
if( pHwData->SurpriseRemove ) return;
@ -270,43 +270,43 @@ void hal_set_accept_beacon( phw_data_t pHwData, u8 enable )
if( !enable )//Due to SME and MLME are not suitable for 35
return;
pWb35Reg->M00_MacControl &= ~0x04000000;//The HW value
reg->M00_MacControl &= ~0x04000000;//The HW value
if( enable )
pWb35Reg->M00_MacControl |= 0x04000000;//The HW value
reg->M00_MacControl |= 0x04000000;//The HW value
Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl );
}
//---------------------------------------------------------------------------------------------------
void hal_set_multicast_address( phw_data_t pHwData, u8 *address, u8 number )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
u8 Byte, Bit;
if( pHwData->SurpriseRemove ) return;
//Erases and refills the card multicast registers. Used when an address
// has been deleted and all bits must be recomputed.
pWb35Reg->M04_MulticastAddress1 = 0;
pWb35Reg->M08_MulticastAddress2 = 0;
reg->M04_MulticastAddress1 = 0;
reg->M08_MulticastAddress2 = 0;
while( number )
{
number--;
CardGetMulticastBit( (address+(number*ETH_LENGTH_OF_ADDRESS)), &Byte, &Bit);
pWb35Reg->Multicast[Byte] |= Bit;
reg->Multicast[Byte] |= Bit;
}
// Updating register
Wb35Reg_BurstWrite( pHwData, 0x0804, (u32 *)pWb35Reg->Multicast, 2, AUTO_INCREMENT );
Wb35Reg_BurstWrite( pHwData, 0x0804, (u32 *)reg->Multicast, 2, AUTO_INCREMENT );
}
//---------------------------------------------------------------------------------------------------
u8 hal_get_accept_beacon( phw_data_t pHwData )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
if( pHwData->SurpriseRemove ) return 0;
if( pWb35Reg->M00_MacControl & 0x04000000 )
if( reg->M00_MacControl & 0x04000000 )
return 1;
else
return 0;
@ -320,7 +320,7 @@ unsigned char hal_reset_hardware( phw_data_t pHwData, void* ppa )
void hal_stop( phw_data_t pHwData )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
pHwData->Wb35Rx.rx_halt = 1;
Wb35Rx_stop( pHwData );
@ -328,18 +328,18 @@ void hal_stop( phw_data_t pHwData )
pHwData->Wb35Tx.tx_halt = 1;
Wb35Tx_stop( pHwData );
pWb35Reg->D00_DmaControl &= ~0xc0000000;//Tx Off, Rx Off
Wb35Reg_Write( pHwData, 0x0400, pWb35Reg->D00_DmaControl );
reg->D00_DmaControl &= ~0xc0000000;//Tx Off, Rx Off
Wb35Reg_Write( pHwData, 0x0400, reg->D00_DmaControl );
WbUsb_Stop( pHwData ); // 20051230 Add.4
}
unsigned char hal_idle(phw_data_t pHwData)
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
PWBUSB pWbUsb = &pHwData->WbUsb;
if( !pHwData->SurpriseRemove && ( pWbUsb->DetectCount || pWb35Reg->EP0vm_state!=VM_STOP ) )
if( !pHwData->SurpriseRemove && ( pWbUsb->DetectCount || reg->EP0vm_state!=VM_STOP ) )
return FALSE;
return TRUE;
@ -347,19 +347,19 @@ unsigned char hal_idle(phw_data_t pHwData)
//---------------------------------------------------------------------------------------------------
void hal_set_cwmin( phw_data_t pHwData, u8 cwin_min )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
if( pHwData->SurpriseRemove ) return;
pHwData->cwmin = cwin_min;
pWb35Reg->M2C_MacControl &= ~0x7c00; //bit 10 ~ 14
pWb35Reg->M2C_MacControl |= (pHwData->cwmin<<10);
Wb35Reg_Write( pHwData, 0x082c, pWb35Reg->M2C_MacControl );
reg->M2C_MacControl &= ~0x7c00; //bit 10 ~ 14
reg->M2C_MacControl |= (pHwData->cwmin<<10);
Wb35Reg_Write( pHwData, 0x082c, reg->M2C_MacControl );
}
s32 hal_get_rssi( phw_data_t pHwData, u32 *HalRssiArry, u8 Count )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
R01_DESCRIPTOR r01;
s32 ltmp = 0, tmp;
u8 i;
@ -373,7 +373,7 @@ s32 hal_get_rssi( phw_data_t pHwData, u32 *HalRssiArry, u8 Count )
for (i=0; i<Count; i++)
{
r01.value = HalRssiArry[i];
tmp = ((( r01.R01_AGC_state + pWb35Reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
tmp = ((( r01.R01_AGC_state + reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
ltmp += tmp;
}
ltmp /= Count;
@ -388,7 +388,7 @@ s32 hal_get_rssi( phw_data_t pHwData, u32 *HalRssiArry, u8 Count )
//----------------------------------------------------------------------------------------------------
s32 hal_get_rssi_bss( phw_data_t pHwData, u16 idx, u8 Count )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
R01_DESCRIPTOR r01;
s32 ltmp = 0, tmp;
u8 i, j;
@ -405,7 +405,7 @@ s32 hal_get_rssi_bss( phw_data_t pHwData, u16 idx, u8 Count )
for (i=0; i<Count; i++)
{
r01.value = HalRssiArry[i];
tmp = ((( r01.R01_AGC_state + pWb35Reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
tmp = ((( r01.R01_AGC_state + reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
ltmp += tmp;
}
#else
@ -416,7 +416,7 @@ s32 hal_get_rssi_bss( phw_data_t pHwData, u16 idx, u8 Count )
for (i=0; i<Count; i++)
{
r01.value = psBSS(idx)->HalRssi[j];
tmp = ((( r01.R01_AGC_state + pWb35Reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
tmp = ((( r01.R01_AGC_state + reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
ltmp += tmp;
if (j == 0)
{
@ -444,7 +444,7 @@ void hal_led_control_1a( phw_data_t pHwData )
void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 )
{
PADAPTER Adapter = pHwData->Adapter;
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
u32 LEDSet = (pHwData->SoftwareSet & HAL_LED_SET_MASK) >> HAL_LED_SET_SHIFT;
u8 LEDgray[20] = { 0,3,4,6,8,10,11,12,13,14,15,14,13,12,11,10,8,6,4,2 };
u8 LEDgray2[30] = { 7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,15,14,13,12,11,10,9,8 };
@ -487,21 +487,21 @@ void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 )
}
pHwData->LED_Blinking++;
pWb35Reg->U1BC_LEDConfigure = ltmp;
reg->U1BC_LEDConfigure = ltmp;
if( LEDSet != 7 ) // Only 111 mode has 2 LEDs on PCB.
{
pWb35Reg->U1BC_LEDConfigure |= (ltmp &0xff)<<8; // Copy LED result to each LED control register
pWb35Reg->U1BC_LEDConfigure |= (ltmp &0xff00)>>8;
reg->U1BC_LEDConfigure |= (ltmp &0xff)<<8; // Copy LED result to each LED control register
reg->U1BC_LEDConfigure |= (ltmp &0xff00)>>8;
}
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure );
}
}
else if( pHwData->CurrentRadioSw || pHwData->CurrentRadioHw ) // If radio off
{
if( pWb35Reg->U1BC_LEDConfigure & 0x1010 )
if( reg->U1BC_LEDConfigure & 0x1010 )
{
pWb35Reg->U1BC_LEDConfigure &= ~0x1010;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
reg->U1BC_LEDConfigure &= ~0x1010;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure );
}
}
else
@ -516,15 +516,15 @@ void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 )
{
if( pHwData->LED_Blinking == 0 )
{
pWb35Reg->U1BC_LEDConfigure |= 0x10;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 On
reg->U1BC_LEDConfigure |= 0x10;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 On
pHwData->LED_Blinking = 1;
TimeInterval = 300;
}
else
{
pWb35Reg->U1BC_LEDConfigure &= ~0x10;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
reg->U1BC_LEDConfigure &= ~0x10;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off
pHwData->LED_Blinking = 0;
TimeInterval = 300;
}
@ -532,20 +532,20 @@ void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 )
else
{
//Turn Off LED_0
if( pWb35Reg->U1BC_LEDConfigure & 0x10 )
if( reg->U1BC_LEDConfigure & 0x10 )
{
pWb35Reg->U1BC_LEDConfigure &= ~0x10;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
reg->U1BC_LEDConfigure &= ~0x10;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off
}
}
}
else
{
// Turn On LED_0
if( (pWb35Reg->U1BC_LEDConfigure & 0x10) == 0 )
if( (reg->U1BC_LEDConfigure & 0x10) == 0 )
{
pWb35Reg->U1BC_LEDConfigure |= 0x10;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
reg->U1BC_LEDConfigure |= 0x10;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off
}
}
break;
@ -558,16 +558,16 @@ void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 )
{
if( pHwData->LED_Blinking == 0 )
{
pWb35Reg->U1BC_LEDConfigure &= ~0xf;
pWb35Reg->U1BC_LEDConfigure |= 0x10;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 On
reg->U1BC_LEDConfigure &= ~0xf;
reg->U1BC_LEDConfigure |= 0x10;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 On
pHwData->LED_Blinking = 1;
TimeInterval = 300;
}
else
{
pWb35Reg->U1BC_LEDConfigure &= ~0x1f;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
reg->U1BC_LEDConfigure &= ~0x1f;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off
pHwData->LED_Blinking = 0;
TimeInterval = 300;
}
@ -575,26 +575,26 @@ void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 )
else
{
// 20060901 Gray blinking if in disconnect state and not scanning
ltmp = pWb35Reg->U1BC_LEDConfigure;
pWb35Reg->U1BC_LEDConfigure &= ~0x1f;
ltmp = reg->U1BC_LEDConfigure;
reg->U1BC_LEDConfigure &= ~0x1f;
if( LEDgray2[(pHwData->LED_Blinking%30)] )
{
pWb35Reg->U1BC_LEDConfigure |= 0x10;
pWb35Reg->U1BC_LEDConfigure |= LEDgray2[ (pHwData->LED_Blinking%30) ];
reg->U1BC_LEDConfigure |= 0x10;
reg->U1BC_LEDConfigure |= LEDgray2[ (pHwData->LED_Blinking%30) ];
}
pHwData->LED_Blinking++;
if( pWb35Reg->U1BC_LEDConfigure != ltmp )
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
if( reg->U1BC_LEDConfigure != ltmp )
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off
TimeInterval = 100;
}
}
else
{
// Turn On LED_0
if( (pWb35Reg->U1BC_LEDConfigure & 0x10) == 0 )
if( (reg->U1BC_LEDConfigure & 0x10) == 0 )
{
pWb35Reg->U1BC_LEDConfigure |= 0x10;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_0 Off
reg->U1BC_LEDConfigure |= 0x10;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off
}
}
break;
@ -607,15 +607,15 @@ void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 )
{
if( pHwData->LED_Blinking == 0 )
{
pWb35Reg->U1BC_LEDConfigure |= 0x1000;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 On
reg->U1BC_LEDConfigure |= 0x1000;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 On
pHwData->LED_Blinking = 1;
TimeInterval = 300;
}
else
{
pWb35Reg->U1BC_LEDConfigure &= ~0x1000;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 Off
reg->U1BC_LEDConfigure &= ~0x1000;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 Off
pHwData->LED_Blinking = 0;
TimeInterval = 300;
}
@ -623,10 +623,10 @@ void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 )
else
{
//Turn Off LED_1
if( pWb35Reg->U1BC_LEDConfigure & 0x1000 )
if( reg->U1BC_LEDConfigure & 0x1000 )
{
pWb35Reg->U1BC_LEDConfigure &= ~0x1000;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 Off
reg->U1BC_LEDConfigure &= ~0x1000;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 Off
}
}
}
@ -636,10 +636,10 @@ void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 )
if( (OS_CURRENT_RX_BYTE( Adapter ) != pHwData->RxByteCountLast ) ||
(OS_CURRENT_TX_BYTE( Adapter ) != pHwData->TxByteCountLast ) )
{
if( (pWb35Reg->U1BC_LEDConfigure & 0x3000) != 0x3000 )
if( (reg->U1BC_LEDConfigure & 0x3000) != 0x3000 )
{
pWb35Reg->U1BC_LEDConfigure |= 0x3000;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 On
reg->U1BC_LEDConfigure |= 0x3000;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 On
}
// Update variable
@ -650,30 +650,30 @@ void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 )
else
{
// Turn On LED_1 and blinking if transmitting/receiving
if( (pWb35Reg->U1BC_LEDConfigure & 0x3000) != 0x1000 )
if( (reg->U1BC_LEDConfigure & 0x3000) != 0x1000 )
{
pWb35Reg->U1BC_LEDConfigure &= ~0x3000;
pWb35Reg->U1BC_LEDConfigure |= 0x1000;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure ); // LED_1 On
reg->U1BC_LEDConfigure &= ~0x3000;
reg->U1BC_LEDConfigure |= 0x1000;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 On
}
}
}
break;
default: // Default setting. 2 LED be placed on PCB. LED_0: Link On LED_1 Active
if( (pWb35Reg->U1BC_LEDConfigure & 0x3000) != 0x3000 )
if( (reg->U1BC_LEDConfigure & 0x3000) != 0x3000 )
{
pWb35Reg->U1BC_LEDConfigure |= 0x3000;// LED_1 is always on and event enable
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
reg->U1BC_LEDConfigure |= 0x3000;// LED_1 is always on and event enable
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure );
}
if( pHwData->LED_Blinking )
{
// Gray blinking
pWb35Reg->U1BC_LEDConfigure &= ~0x0f;
pWb35Reg->U1BC_LEDConfigure |= 0x10;
pWb35Reg->U1BC_LEDConfigure |= LEDgray[ (pHwData->LED_Blinking-1)%20 ];
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
reg->U1BC_LEDConfigure &= ~0x0f;
reg->U1BC_LEDConfigure |= 0x10;
reg->U1BC_LEDConfigure |= LEDgray[ (pHwData->LED_Blinking-1)%20 ];
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure );
pHwData->LED_Blinking += 2;
if( pHwData->LED_Blinking < 40 )
@ -681,28 +681,28 @@ void hal_led_control( void* S1, phw_data_t pHwData, void* S3, void* S4 )
else
{
pHwData->LED_Blinking = 0; // Stop blinking
pWb35Reg->U1BC_LEDConfigure &= ~0x0f;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
reg->U1BC_LEDConfigure &= ~0x0f;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure );
}
break;
}
if( pHwData->LED_LinkOn )
{
if( !(pWb35Reg->U1BC_LEDConfigure & 0x10) ) // Check the LED_0
if( !(reg->U1BC_LEDConfigure & 0x10) ) // Check the LED_0
{
//Try to turn ON LED_0 after gray blinking
pWb35Reg->U1BC_LEDConfigure |= 0x10;
reg->U1BC_LEDConfigure |= 0x10;
pHwData->LED_Blinking = 1; //Start blinking
TimeInterval = 50;
}
}
else
{
if( pWb35Reg->U1BC_LEDConfigure & 0x10 ) // Check the LED_0
if( reg->U1BC_LEDConfigure & 0x10 ) // Check the LED_0
{
pWb35Reg->U1BC_LEDConfigure &= ~0x10;
Wb35Reg_Write( pHwData, 0x03bc, pWb35Reg->U1BC_LEDConfigure );
reg->U1BC_LEDConfigure &= ~0x10;
Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure );
}
}
break;
@ -744,28 +744,28 @@ void hal_reset_counter( phw_data_t pHwData )
void hal_set_radio_mode( phw_data_t pHwData, unsigned char radio_off)
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
if( pHwData->SurpriseRemove ) return;
if (radio_off) //disable Baseband receive off
{
pHwData->CurrentRadioSw = 1; // off
pWb35Reg->M24_MacControl &= 0xffffffbf;
reg->M24_MacControl &= 0xffffffbf;
}
else
{
pHwData->CurrentRadioSw = 0; // on
pWb35Reg->M24_MacControl |= 0x00000040;
reg->M24_MacControl |= 0x00000040;
}
Wb35Reg_Write( pHwData, 0x0824, pWb35Reg->M24_MacControl );
Wb35Reg_Write( pHwData, 0x0824, reg->M24_MacControl );
}
u8 hal_get_antenna_number( phw_data_t pHwData )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
if ((pWb35Reg->BB2C & BIT(11)) == 0)
if ((reg->BB2C & BIT(11)) == 0)
return 0;
else
return 1;
@ -774,14 +774,14 @@ u8 hal_get_antenna_number( phw_data_t pHwData )
void hal_set_antenna_number( phw_data_t pHwData, u8 number )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
if (number == 1) {
pWb35Reg->BB2C |= BIT(11);
reg->BB2C |= BIT(11);
} else {
pWb35Reg->BB2C &= ~BIT(11);
reg->BB2C &= ~BIT(11);
}
Wb35Reg_Write( pHwData, 0x102c, pWb35Reg->BB2C );
Wb35Reg_Write( pHwData, 0x102c, reg->BB2C );
#ifdef _PE_STATE_DUMP_
WBDEBUG(("Current antenna number : %d\n", number));
#endif
@ -791,13 +791,13 @@ void hal_set_antenna_number( phw_data_t pHwData, u8 number )
//0 : radio on; 1: radio off
u8 hal_get_hw_radio_off( phw_data_t pHwData )
{
PWB35REG pWb35Reg = &pHwData->Wb35Reg;
struct wb35_reg *reg = &pHwData->reg;
if( pHwData->SurpriseRemove ) return 1;
//read the bit16 of register U1B0
Wb35Reg_Read( pHwData, 0x3b0, &pWb35Reg->U1B0 );
if ((pWb35Reg->U1B0 & 0x00010000)) {
Wb35Reg_Read( pHwData, 0x3b0, &reg->U1B0 );
if ((reg->U1B0 & 0x00010000)) {
pHwData->CurrentRadioHw = 1;
return 1;
} else {

2
drivers/staging/winbond/wbhal_f.h
View File

@ -79,7 +79,7 @@ void hal_descriptor_indicate( phw_data_t pHwData, PDESCRIPTOR pDes );
u8 hal_get_antenna_number( phw_data_t pHwData );
void hal_set_antenna_number( phw_data_t pHwData, u8 number );
u32 hal_get_bss_pk_cnt( phw_data_t pHwData );
#define hal_get_region_from_EEPROM( _A ) ( (_A)->Wb35Reg.EEPROMRegion )
#define hal_get_region_from_EEPROM( _A ) ( (_A)->reg.EEPROMRegion )
void hal_set_accept_promiscuous ( phw_data_t pHwData, u8 enable);
#define hal_get_tx_buffer( _A, _B ) Wb35Tx_get_tx_buffer( _A, _B )
u8 hal_get_hw_radio_off ( phw_data_t pHwData );

2
drivers/staging/winbond/wbhal_s.h
View File

@ -506,7 +506,7 @@ typedef struct _HW_DATA_T
// Variable for each module
//========================================================================
WBUSB WbUsb; // Need WbUsb.h
WB35REG Wb35Reg; // Need Wb35Reg.h
struct wb35_reg reg; // Need Wb35Reg.h
WB35TX Wb35Tx; // Need Wb35Tx.h
WB35RX Wb35Rx; // Need Wb35Rx.h