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i.MX fixes for 4.18: 

- Fix i.MX6SX PCIe MSI interrupt number, so that MSI IRQs can be
    properly propagated to the upstream interrupt controller.
  - Fix GPCv2 MIPI/PCIe/USB_HSIC's PGC offset.  The values in Reference
    Manual are incorrect.
  - Correct SDMA setting for i.MX6Q SPI5 device to fix the issue, that
    the SPI controller RX FIFO was not empty after a DMA transfer, and
    the driver gets stuck in the next PIO transfer when reading one word
    more than expected.
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Merge tag 'imx-fixes-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes

i.MX fixes for 4.18:
 - Fix i.MX6SX PCIe MSI interrupt number, so that MSI IRQs can be
   properly propagated to the upstream interrupt controller.
 - Fix GPCv2 MIPI/PCIe/USB_HSIC's PGC offset.  The values in Reference
   Manual are incorrect.
 - Correct SDMA setting for i.MX6Q SPI5 device to fix the issue, that
   the SPI controller RX FIFO was not empty after a DMA transfer, and
   the driver gets stuck in the next PIO transfer when reading one word
   more than expected.

* tag 'imx-fixes-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: dts: imx6sx: fix irq for pcie bridge
  soc: imx: gpcv2: correct PGC offset
  ARM: dts: imx6q: Use correct SDMA script for SPI5 core

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-06-23 10:17:38 -07:00
parent cb04a79445 1bcfe05640
commit 652caf4ab1
3 changed files with 11 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/imx6q.dtsi
View File

@ -90,7 +90,7 @@ ecspi5: ecspi@2018000 {
clocks = <&clks IMX6Q_CLK_ECSPI5>,
<&clks IMX6Q_CLK_ECSPI5>;
clock-names = "ipg", "per";
dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
dma-names = "rx", "tx";
status = "disabled";
};

2
arch/arm/boot/dts/imx6sx.dtsi
View File

@ -1344,7 +1344,7 @@ pcie: pcie@8ffc000 {
ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;

13
drivers/soc/imx/gpcv2.c
View File

@ -39,10 +39,15 @@
#define GPC_M4_PU_PDN_FLG 0x1bc
#define PGC_MIPI 4
#define PGC_PCIE 5
#define PGC_USB_HSIC 8
/*
* The PGC offset values in Reference Manual
* (Rev. 1, 01/2018 and the older ones) GPC chapter's
* GPC_PGC memory map are incorrect, below offset
* values are from design RTL.
*/
#define PGC_MIPI 16
#define PGC_PCIE 17
#define PGC_USB_HSIC 20
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)