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ARM64: DT: Hisilicon SoC DT updates for 4.11 

- Add binding for Hi3660 SoC and HiKey960 Board
 - Add binding for ARM Cortex-A73
 - Add dts files for HiKey960 development board
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Merge tag 'hisi-arm64-dt-for-4.11' of git://github.com/hisilicon/linux-hisi into next/dt64

ARM64: DT: Hisilicon SoC DT updates for 4.11

- Add binding for Hi3660 SoC and HiKey960 Board
- Add binding for ARM Cortex-A73
- Add dts files for HiKey960 development board

* tag 'hisi-arm64-dt-for-4.11' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: Add dts files for Hisilicon Hi3660 SoC
  dt-bindings: Add a support cpu type for cortex-a73
  document: dt: add binding for Hi3660 SoC

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2017-01-29 17:28:40 -08:00
parent 5ee3dd850c 35ca816813
commit 656b532ffc
5 changed files with 199 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/cpus.txt
View File

@ -158,6 +158,7 @@ nodes to be present and contain the properties described below.
"arm,cortex-a53"
"arm,cortex-a57"
"arm,cortex-a72"
"arm,cortex-a73"
"arm,cortex-m0"
"arm,cortex-m0+"
"arm,cortex-m1"

4
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
View File

@ -1,5 +1,9 @@
Hisilicon Platforms Device Tree Bindings
----------------------------------------------------
Hi3660 SoC
Required root node properties:
- compatible = "hisilicon,hi3660";
Hi4511 Board
Required root node properties:
- compatible = "hisilicon,hi3620-hi4511";

1
arch/arm64/boot/dts/hisilicon/Makefile
View File

@ -1,3 +1,4 @@
dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb

33
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts Normal file
View File

@ -0,0 +1,33 @@
/*
* dts file for Hisilicon HiKey960 Development Board
*
* Copyright (C) 2016, Hisilicon Ltd.
*
*/
/dts-v1/;
#include "hi3660.dtsi"
/ {
model = "HiKey960";
compatible = "hisilicon,hi3660";
aliases {
serial5 = &uart5; /* console UART */
};
chosen {
stdout-path = "serial5:115200n8";
};
memory@0 {
device_type = "memory";
/* rewrite this at bootloader */
reg = <0x0 0x0 0x0 0x0>;
};
};
&uart5 {
status = "okay";
};

160
arch/arm64/boot/dts/hisilicon/hi3660.dtsi Normal file
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@ -0,0 +1,160 @@
/*
* dts file for Hisilicon Hi3660 SoC
*
* Copyright (C) 2016, Hisilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "hisilicon,hi3660";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
};
cpu4: cpu@100 {
compatible = "arm,cortex-a73", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "psci";
};
cpu5: cpu@101 {
compatible = "arm,cortex-a73", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "psci";
};
cpu6: cpu@102 {
compatible = "arm,cortex-a73", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "psci";
};
cpu7: cpu@103 {
compatible = "arm,cortex-a73", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "psci";
};
};
gic: interrupt-controller@e82b0000 {
compatible = "arm,gic-400";
reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
<0x0 0xe82b2000 0 0x2000>, /* GICC */
<0x0 0xe82b4000 0 0x2000>, /* GICH */
<0x0 0xe82b6000 0 0x2000>; /* GICV */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_HIGH)>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
fixed_uart5: fixed_19_2M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "fixed:uart5";
};
uart5: uart@fdf05000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf05000 0x0 0x1000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&fixed_uart5 &fixed_uart5>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};