mirror of https://gitee.com/openkylin/linux.git
irqchip core changes for v4.8
- bcm283x avoid handle_IRQ - misc - Fix sparse warnings on __iomem - Fix static functions - Fix missing includes - Replace __raw IO accessors to support big endian -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJXbDUMAAoJEP45WPkGe8ZntvgP/1/0UqGB3Y3hG1HsmBCe6Up7 OkaFMiYJhmsl9MbjZBnV2b3UiuFXIbQPAQaUvUJYvtzpQ8FqT6RpbS5hLe+5WwSk hnt6gUS8nk76U2O3HY156STa2bRFvVEhpUJqpyiKh91mtT7tA34M3MJraxOIuZIv SgkX2maab0uC68Kg/2HSWwIUnV9arcBZ2zhUAjDimYVI6P2C5H2EQu2JrVcRxhXG 8TgMDMFfNWIfD5x9Globs4AHTJAfwBOHVOTzt944E0o5jAF8CF+SC0+XuyiFAVV9 GETVNsUI0zjVoAHTEOV40IJ/A7mrEOXmmKpgYljazOoN9T51RdFLGzImWe/80N3p sAoAtNYjToWRoQJMbouGVh/9d6y5jTxTFCBiC/oAD4/H4sQfC/O9/U2n0oKXKL/6 bJnhErR3cOImELSk4gVDQ6cs5n1g8pKZsh7ABIodd+ZwXVolnvqaiEsmiiW13O2p x6B+94FkdbyTb8ZBJ8nWmvHN/wid4Qf0ulQSPxD84jNd88HDAe8kyqqSEeiM09IE YzXzD3UcQ/T4AOLxJBVcGySQfgBlxgmKCQFctEVAboG9Px38P/VAl7J0BjDIqbec UV/Er/RQnvVIz6q9ajx2WVPvRwyBpMK/0HYbiCp+Bfi3yKhA3OoV/AUjQMxTC9Jn 4/c/W8301D0dxiDBmmDG =lGrP -----END PGP SIGNATURE----- Merge tag 'irqchip-core-4.8' of git://git.infradead.org/users/jcooper/linux into irq/core Pull irqchip core changes from Jason Cooper: - bcm283x avoid handle_IRQ - Fix sparse warnings on __iomem - Fix static functions - Fix missing includes - Replace __raw IO accessors to support big endian
This commit is contained in:
commit
6589c1caa7
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@ -55,14 +55,14 @@ static void combiner_mask_irq(struct irq_data *data)
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{
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u32 mask = 1 << (data->hwirq % 32);
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__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
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writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
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}
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static void combiner_unmask_irq(struct irq_data *data)
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{
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u32 mask = 1 << (data->hwirq % 32);
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__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
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writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET);
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}
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static void combiner_handle_cascade_irq(struct irq_desc *desc)
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@ -75,7 +75,7 @@ static void combiner_handle_cascade_irq(struct irq_desc *desc)
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chained_irq_enter(chip, desc);
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spin_lock(&irq_controller_lock);
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status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
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status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS);
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spin_unlock(&irq_controller_lock);
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status &= chip_data->irq_mask;
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@ -135,7 +135,7 @@ static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
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combiner_data->parent_irq = irq;
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/* Disable all interrupts */
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__raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
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writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
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}
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static int combiner_irq_domain_xlate(struct irq_domain *d,
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@ -218,7 +218,7 @@ static int combiner_suspend(void)
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for (i = 0; i < max_nr; i++)
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combiner_data[i].pm_save =
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__raw_readl(combiner_data[i].base + COMBINER_ENABLE_SET);
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readl_relaxed(combiner_data[i].base + COMBINER_ENABLE_SET);
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return 0;
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}
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@ -235,9 +235,9 @@ static void combiner_resume(void)
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int i;
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for (i = 0; i < max_nr; i++) {
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__raw_writel(combiner_data[i].irq_mask,
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writel_relaxed(combiner_data[i].irq_mask,
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combiner_data[i].base + COMBINER_ENABLE_CLEAR);
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__raw_writel(combiner_data[i].pm_save,
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writel_relaxed(combiner_data[i].pm_save,
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combiner_data[i].base + COMBINER_ENABLE_SET);
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}
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}
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@ -541,7 +541,7 @@ static void armada_370_xp_mpic_resume(void)
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writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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}
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struct syscore_ops armada_370_xp_mpic_syscore_ops = {
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static struct syscore_ops armada_370_xp_mpic_syscore_ops = {
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.suspend = armada_370_xp_mpic_suspend,
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.resume = armada_370_xp_mpic_resume,
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};
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@ -52,7 +52,6 @@
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#include <linux/irqdomain.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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/* Put the bank and irq (32 bits) into the hwirq */
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#define MAKE_HWIRQ(b, n) ((b << 5) | (n))
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@ -242,7 +241,7 @@ static void __exception_irq_entry bcm2835_handle_irq(
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u32 hwirq;
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while ((hwirq = get_next_armctrl_hwirq()) != ~0)
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handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs);
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handle_domain_irq(intc.domain, hwirq, regs);
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}
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static void bcm2836_chained_handle_irq(struct irq_desc *desc)
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@ -180,7 +180,7 @@ __exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
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} else if (stat) {
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u32 hwirq = ffs(stat) - 1;
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handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs);
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handle_domain_irq(intc.domain, hwirq, regs);
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}
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}
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@ -224,8 +224,8 @@ static struct notifier_block bcm2836_arm_irqchip_cpu_notifier = {
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};
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#ifdef CONFIG_ARM
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int __init bcm2836_smp_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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static int __init bcm2836_smp_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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unsigned long secondary_startup_phys =
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(unsigned long)virt_to_phys((void *)secondary_startup);
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@ -215,7 +215,7 @@ static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
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return 0;
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}
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int __init bcm7120_l2_intc_probe(struct device_node *dn,
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static int __init bcm7120_l2_intc_probe(struct device_node *dn,
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struct device_node *parent,
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int (*iomap_regs_fn)(struct device_node *,
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struct bcm7120_l2_intc_data *),
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@ -339,15 +339,15 @@ int __init bcm7120_l2_intc_probe(struct device_node *dn,
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return ret;
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}
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int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
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struct device_node *parent)
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static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
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struct device_node *parent)
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{
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return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
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"BCM7120 L2");
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}
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int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
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struct device_node *parent)
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static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
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struct device_node *parent)
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{
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return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
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"BCM3380 L2");
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@ -112,8 +112,8 @@ static void brcmstb_l2_intc_resume(struct irq_data *d)
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irq_gc_unlock(gc);
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}
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int __init brcmstb_l2_intc_of_init(struct device_node *np,
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struct device_node *parent)
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static int __init brcmstb_l2_intc_of_init(struct device_node *np,
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struct device_node *parent)
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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struct brcmstb_l2_intc_data *data;
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@ -24,6 +24,7 @@
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#include <linux/of_pci.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/irqchip/arm-gic.h>
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/*
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* MSI_TYPER:
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@ -23,6 +23,8 @@
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip/irq-omap-intc.h>
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/* Define these here for now until we drop all board-files */
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#define OMAP24XX_IC_BASE 0x480fe000
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#define OMAP34XX_IC_BASE 0x48200000
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@ -92,9 +92,9 @@ static void s3c_irq_mask(struct irq_data *data)
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unsigned long mask;
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unsigned int irqno;
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mask = __raw_readl(intc->reg_mask);
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mask = readl_relaxed(intc->reg_mask);
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mask |= (1UL << irq_data->offset);
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__raw_writel(mask, intc->reg_mask);
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writel_relaxed(mask, intc->reg_mask);
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if (parent_intc) {
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parent_data = &parent_intc->irqs[irq_data->parent_irq];
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@ -119,9 +119,9 @@ static void s3c_irq_unmask(struct irq_data *data)
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unsigned long mask;
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unsigned int irqno;
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mask = __raw_readl(intc->reg_mask);
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mask = readl_relaxed(intc->reg_mask);
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mask &= ~(1UL << irq_data->offset);
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__raw_writel(mask, intc->reg_mask);
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writel_relaxed(mask, intc->reg_mask);
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if (parent_intc) {
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irqno = irq_find_mapping(parent_intc->domain,
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@ -136,9 +136,9 @@ static inline void s3c_irq_ack(struct irq_data *data)
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struct s3c_irq_intc *intc = irq_data->intc;
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unsigned long bitval = 1UL << irq_data->offset;
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__raw_writel(bitval, intc->reg_pending);
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writel_relaxed(bitval, intc->reg_pending);
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if (intc->reg_intpnd)
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__raw_writel(bitval, intc->reg_intpnd);
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writel_relaxed(bitval, intc->reg_intpnd);
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}
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static int s3c_irq_type(struct irq_data *data, unsigned int type)
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unsigned long newvalue = 0, value;
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/* Set the GPIO to external interrupt mode */
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value = __raw_readl(gpcon_reg);
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value = readl_relaxed(gpcon_reg);
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value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
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__raw_writel(value, gpcon_reg);
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writel_relaxed(value, gpcon_reg);
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/* Set the external interrupt to pointed trigger type */
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switch (type)
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return -EINVAL;
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}
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value = __raw_readl(extint_reg);
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value = readl_relaxed(extint_reg);
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value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
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__raw_writel(value, extint_reg);
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writel_relaxed(value, extint_reg);
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return 0;
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}
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@ -315,8 +315,8 @@ static void s3c_irq_demux(struct irq_desc *desc)
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chained_irq_enter(chip, desc);
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src = __raw_readl(sub_intc->reg_pending);
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msk = __raw_readl(sub_intc->reg_mask);
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src = readl_relaxed(sub_intc->reg_pending);
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msk = readl_relaxed(sub_intc->reg_mask);
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src &= ~msk;
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src &= irq_data->sub_bits;
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@ -337,7 +337,7 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
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int pnd;
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int offset;
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pnd = __raw_readl(intc->reg_intpnd);
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pnd = readl_relaxed(intc->reg_intpnd);
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if (!pnd)
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return false;
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@ -352,7 +352,7 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
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*
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* Thanks to Klaus, Shannon, et al for helping to debug this problem
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*/
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offset = __raw_readl(intc->reg_intpnd + 4);
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offset = readl_relaxed(intc->reg_intpnd + 4);
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/* Find the bit manually, when the offset is wrong.
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* The pending register only ever contains the one bit of the next
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@ -406,7 +406,7 @@ int s3c24xx_set_fiq(unsigned int irq, bool on)
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intmod = 0;
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}
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__raw_writel(intmod, S3C2410_INTMOD);
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writel_relaxed(intmod, S3C2410_INTMOD);
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return 0;
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}
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@ -508,14 +508,14 @@ static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
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last = 0;
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for (i = 0; i < 4; i++) {
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pend = __raw_readl(reg_source);
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pend = readl_relaxed(reg_source);
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if (pend == 0 || pend == last)
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break;
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__raw_writel(pend, intc->reg_pending);
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writel_relaxed(pend, intc->reg_pending);
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if (intc->reg_intpnd)
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__raw_writel(pend, intc->reg_intpnd);
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writel_relaxed(pend, intc->reg_intpnd);
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pr_info("irq: clearing pending status %08x\n", (int)pend);
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last = pend;
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@ -29,6 +29,11 @@
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static struct irq_domain *sirfsoc_irqdomain;
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static void __iomem *sirfsoc_irq_get_regbase(void)
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{
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return (void __iomem __force *)sirfsoc_irqdomain->host_data;
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}
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static __init void sirfsoc_alloc_gc(void __iomem *base)
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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@ -53,7 +58,7 @@ static __init void sirfsoc_alloc_gc(void __iomem *base)
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static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
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{
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void __iomem *base = sirfsoc_irqdomain->host_data;
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void __iomem *base = sirfsoc_irq_get_regbase();
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u32 irqstat;
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irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
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@ -94,7 +99,7 @@ static struct sirfsoc_irq_status sirfsoc_irq_st;
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static int sirfsoc_irq_suspend(void)
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{
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void __iomem *base = sirfsoc_irqdomain->host_data;
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void __iomem *base = sirfsoc_irq_get_regbase();
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sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
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sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
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@ -106,7 +111,7 @@ static int sirfsoc_irq_suspend(void)
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static void sirfsoc_irq_resume(void)
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{
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void __iomem *base = sirfsoc_irqdomain->host_data;
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void __iomem *base = sirfsoc_irq_get_regbase();
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writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
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writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
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@ -90,7 +90,7 @@ static struct tegra_ictlr_info *lic;
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static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long reg)
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{
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void __iomem *base = d->chip_data;
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void __iomem *base = (void __iomem __force *)d->chip_data;
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u32 mask;
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mask = BIT(d->hwirq % 32);
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@ -266,7 +266,7 @@ static int tegra_ictlr_domain_alloc(struct irq_domain *domain,
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irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
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&tegra_ictlr_chip,
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info->base[ictlr]);
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(void __force *)info->base[ictlr]);
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}
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parent_fwspec = *fwspec;
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|
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|
@ -167,7 +167,7 @@ static int vic_suspend(void)
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return 0;
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}
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struct syscore_ops vic_syscore_ops = {
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static struct syscore_ops vic_syscore_ops = {
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.suspend = vic_suspend,
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.resume = vic_resume,
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};
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|
@ -517,7 +517,8 @@ int __init vic_init_cascaded(void __iomem *base, unsigned int parent_irq,
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EXPORT_SYMBOL_GPL(vic_init_cascaded);
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#ifdef CONFIG_OF
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int __init vic_of_init(struct device_node *node, struct device_node *parent)
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static int __init vic_of_init(struct device_node *node,
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struct device_node *parent)
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{
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void __iomem *regs;
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u32 interrupt_mask = ~0;
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|
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