mirror of https://gitee.com/openkylin/linux.git
drm/i915: convert the IRQ initialization functions to intel_uncore
The IRQ initialization helpers are simple and self-contained. Continue the transition started in the recent uncore rework to get us rid of I915_READ/WRITE and the implicit dev_priv variables. While the implicit dev_priv is removed from the IRQ initialization helpers, we didn't get rid of them in the macro callers. Doing that should be very simple now. v2: Rebase on top of the new patches. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1) Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190410235344.31199-5-paulo.r.zanoni@intel.com
This commit is contained in:
Paulo Zanoni
parent
9d9523d8c1
commit
65f42cdc6e
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@ -136,121 +136,120 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
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[HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
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};
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static void gen3_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr,
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static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
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i915_reg_t iir, i915_reg_t ier)
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{
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I915_WRITE(imr, 0xffffffff);
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POSTING_READ(imr);
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intel_uncore_write(uncore, imr, 0xffffffff);
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intel_uncore_posting_read(uncore, imr);
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I915_WRITE(ier, 0);
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intel_uncore_write(uncore, ier, 0);
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/* IIR can theoretically queue up two events. Be paranoid. */
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I915_WRITE(iir, 0xffffffff);
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POSTING_READ(iir);
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I915_WRITE(iir, 0xffffffff);
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POSTING_READ(iir);
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intel_uncore_write(uncore, iir, 0xffffffff);
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intel_uncore_posting_read(uncore, iir);
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intel_uncore_write(uncore, iir, 0xffffffff);
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intel_uncore_posting_read(uncore, iir);
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}
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static void gen2_irq_reset(struct drm_i915_private *dev_priv)
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static void gen2_irq_reset(struct intel_uncore *uncore)
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{
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I915_WRITE16(GEN2_IMR, 0xffff);
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POSTING_READ16(GEN2_IMR);
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intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
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intel_uncore_posting_read16(uncore, GEN2_IMR);
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I915_WRITE16(GEN2_IER, 0);
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intel_uncore_write16(uncore, GEN2_IER, 0);
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/* IIR can theoretically queue up two events. Be paranoid. */
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I915_WRITE16(GEN2_IIR, 0xffff);
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POSTING_READ16(GEN2_IIR);
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I915_WRITE16(GEN2_IIR, 0xffff);
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POSTING_READ16(GEN2_IIR);
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intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
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intel_uncore_posting_read16(uncore, GEN2_IIR);
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intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
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intel_uncore_posting_read16(uncore, GEN2_IIR);
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}
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#define GEN8_IRQ_RESET_NDX(type, which) \
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({ \
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unsigned int which_ = which; \
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gen3_irq_reset(dev_priv, GEN8_##type##_IMR(which_), \
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gen3_irq_reset(&dev_priv->uncore, GEN8_##type##_IMR(which_), \
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GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
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})
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#define GEN3_IRQ_RESET(type) \
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gen3_irq_reset(dev_priv, type##IMR, type##IIR, type##IER)
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gen3_irq_reset(&dev_priv->uncore, type##IMR, type##IIR, type##IER)
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#define GEN2_IRQ_RESET() \
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gen2_irq_reset(dev_priv)
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gen2_irq_reset(&dev_priv->uncore)
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/*
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* We should clear IMR at preinstall/uninstall, and just check at postinstall.
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*/
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static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
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i915_reg_t reg)
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static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
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{
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u32 val = I915_READ(reg);
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u32 val = intel_uncore_read(uncore, reg);
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if (val == 0)
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return;
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WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
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i915_mmio_reg_offset(reg), val);
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I915_WRITE(reg, 0xffffffff);
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POSTING_READ(reg);
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I915_WRITE(reg, 0xffffffff);
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POSTING_READ(reg);
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intel_uncore_write(uncore, reg, 0xffffffff);
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intel_uncore_posting_read(uncore, reg);
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intel_uncore_write(uncore, reg, 0xffffffff);
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intel_uncore_posting_read(uncore, reg);
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}
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static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv)
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static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
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{
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u16 val = I915_READ16(GEN2_IIR);
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u16 val = intel_uncore_read16(uncore, GEN2_IIR);
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if (val == 0)
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return;
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WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
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i915_mmio_reg_offset(GEN2_IIR), val);
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I915_WRITE16(GEN2_IIR, 0xffff);
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POSTING_READ16(GEN2_IIR);
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I915_WRITE16(GEN2_IIR, 0xffff);
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POSTING_READ16(GEN2_IIR);
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intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
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intel_uncore_posting_read16(uncore, GEN2_IIR);
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intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
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intel_uncore_posting_read16(uncore, GEN2_IIR);
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}
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static void gen3_irq_init(struct drm_i915_private *dev_priv,
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static void gen3_irq_init(struct intel_uncore *uncore,
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i915_reg_t imr, u32 imr_val,
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i915_reg_t ier, u32 ier_val,
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i915_reg_t iir)
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{
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gen3_assert_iir_is_zero(dev_priv, iir);
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gen3_assert_iir_is_zero(uncore, iir);
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I915_WRITE(ier, ier_val);
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I915_WRITE(imr, imr_val);
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POSTING_READ(imr);
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intel_uncore_write(uncore, ier, ier_val);
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intel_uncore_write(uncore, imr, imr_val);
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intel_uncore_posting_read(uncore, imr);
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}
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static void gen2_irq_init(struct drm_i915_private *dev_priv,
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static void gen2_irq_init(struct intel_uncore *uncore,
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u32 imr_val, u32 ier_val)
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{
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gen2_assert_iir_is_zero(dev_priv);
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gen2_assert_iir_is_zero(uncore);
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I915_WRITE16(GEN2_IER, ier_val);
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I915_WRITE16(GEN2_IMR, imr_val);
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POSTING_READ16(GEN2_IMR);
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intel_uncore_write16(uncore, GEN2_IER, ier_val);
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intel_uncore_write16(uncore, GEN2_IMR, imr_val);
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intel_uncore_posting_read16(uncore, GEN2_IMR);
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}
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#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) \
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({ \
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unsigned int which_ = which; \
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gen3_irq_init(dev_priv, \
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gen3_irq_init(&dev_priv->uncore, \
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GEN8_##type##_IMR(which_), imr_val, \
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GEN8_##type##_IER(which_), ier_val, \
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GEN8_##type##_IIR(which_)); \
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})
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#define GEN3_IRQ_INIT(type, imr_val, ier_val) \
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gen3_irq_init(dev_priv, \
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gen3_irq_init(&dev_priv->uncore, \
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type##IMR, imr_val, \
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type##IER, ier_val, \
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type##IIR)
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#define GEN2_IRQ_INIT(imr_val, ier_val) \
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gen2_irq_init(dev_priv, imr_val, ier_val)
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gen2_irq_init(&dev_priv->uncore, imr_val, ier_val)
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static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
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static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
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@ -3884,7 +3883,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
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else
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mask = SDE_GMBUS_CPT;
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gen3_assert_iir_is_zero(dev_priv, SDEIIR);
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gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
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I915_WRITE(SDEIMR, ~mask);
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if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
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@ -3953,7 +3952,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
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}
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if (IS_HASWELL(dev_priv)) {
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gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
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gen3_assert_iir_is_zero(&dev_priv->uncore, EDP_PSR_IIR);
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intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
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display_mask |= DE_EDP_PSR_INT_HSW;
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}
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@ -4099,7 +4098,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
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else if (IS_BROADWELL(dev_priv))
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de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
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gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
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gen3_assert_iir_is_zero(&dev_priv->uncore, EDP_PSR_IIR);
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intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
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for_each_pipe(dev_priv, pipe) {
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@ -4183,7 +4182,7 @@ static void icp_irq_postinstall(struct drm_device *dev)
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I915_WRITE(SDEIER, 0xffffffff);
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POSTING_READ(SDEIER);
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gen3_assert_iir_is_zero(dev_priv, SDEIIR);
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gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
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I915_WRITE(SDEIMR, ~mask);
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icp_hpd_detection_setup(dev_priv);
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