mirror of https://gitee.com/openkylin/linux.git
irqchip/xilinx: Add support for multiple instances
Added support for cascaded interrupt controllers. Following cascaded configurations have been tested, - peripheral->xilinx-intc->xilinx-intc->gic->Cortexa53 processor on zcu102 board - peripheral->xilinx-intc->xilinx-intc->microblaze processor on kcu105 board Signed-off-by: Mubin Sayyed <mubin.usman.sayyed@xilinx.com> Signed-off-by: Anirudha Sarangi <anirudha.sarangi@xilinx.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200317125600.15913-2-mubin.usman.sayyed@xilinx.com
This commit is contained in:
Mubin Sayyed
Marc Zyngier
parent
7d4cac5b7c
commit
67862a3c47
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@ -38,29 +38,31 @@ struct xintc_irq_chip {
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void __iomem *base;
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struct irq_domain *root_domain;
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u32 intr_mask;
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u32 nr_irq;
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};
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static struct xintc_irq_chip *xintc_irqc;
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static struct xintc_irq_chip *primary_intc;
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static void xintc_write(int reg, u32 data)
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static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data)
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{
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if (static_branch_unlikely(&xintc_is_be))
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iowrite32be(data, xintc_irqc->base + reg);
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iowrite32be(data, irqc->base + reg);
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else
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iowrite32(data, xintc_irqc->base + reg);
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iowrite32(data, irqc->base + reg);
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}
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static unsigned int xintc_read(int reg)
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static u32 xintc_read(struct xintc_irq_chip *irqc, int reg)
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{
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if (static_branch_unlikely(&xintc_is_be))
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return ioread32be(xintc_irqc->base + reg);
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return ioread32be(irqc->base + reg);
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else
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return ioread32(xintc_irqc->base + reg);
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return ioread32(irqc->base + reg);
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}
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static void intc_enable_or_unmask(struct irq_data *d)
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{
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unsigned long mask = 1 << d->hwirq;
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struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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unsigned long mask = BIT(d->hwirq);
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pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq);
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@ -69,30 +71,35 @@ static void intc_enable_or_unmask(struct irq_data *d)
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* acks the irq before calling the interrupt handler
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*/
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if (irqd_is_level_type(d))
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xintc_write(IAR, mask);
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xintc_write(irqc, IAR, mask);
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xintc_write(SIE, mask);
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xintc_write(irqc, SIE, mask);
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}
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static void intc_disable_or_mask(struct irq_data *d)
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{
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struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
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xintc_write(CIE, 1 << d->hwirq);
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xintc_write(irqc, CIE, BIT(d->hwirq));
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}
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static void intc_ack(struct irq_data *d)
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{
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struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
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xintc_write(IAR, 1 << d->hwirq);
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xintc_write(irqc, IAR, BIT(d->hwirq));
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}
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static void intc_mask_ack(struct irq_data *d)
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{
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unsigned long mask = 1 << d->hwirq;
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struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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unsigned long mask = BIT(d->hwirq);
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pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
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xintc_write(CIE, mask);
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xintc_write(IAR, mask);
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xintc_write(irqc, CIE, mask);
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xintc_write(irqc, IAR, mask);
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}
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static struct irq_chip intc_dev = {
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@ -103,13 +110,28 @@ static struct irq_chip intc_dev = {
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.irq_mask_ack = intc_mask_ack,
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};
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static unsigned int xintc_get_irq_local(struct xintc_irq_chip *irqc)
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{
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unsigned int irq = 0;
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u32 hwirq;
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hwirq = xintc_read(irqc, IVR);
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if (hwirq != -1U)
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irq = irq_find_mapping(irqc->root_domain, hwirq);
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pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
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return irq;
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}
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unsigned int xintc_get_irq(void)
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{
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unsigned int hwirq, irq = -1;
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unsigned int irq = -1;
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u32 hwirq;
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hwirq = xintc_read(IVR);
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hwirq = xintc_read(primary_intc, IVR);
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if (hwirq != -1U)
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irq = irq_find_mapping(xintc_irqc->root_domain, hwirq);
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irq = irq_find_mapping(primary_intc->root_domain, hwirq);
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pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
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@ -118,15 +140,18 @@ unsigned int xintc_get_irq(void)
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static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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if (xintc_irqc->intr_mask & (1 << hw)) {
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struct xintc_irq_chip *irqc = d->host_data;
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if (irqc->intr_mask & BIT(hw)) {
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irq_set_chip_and_handler_name(irq, &intc_dev,
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handle_edge_irq, "edge");
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handle_edge_irq, "edge");
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irq_clear_status_flags(irq, IRQ_LEVEL);
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} else {
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irq_set_chip_and_handler_name(irq, &intc_dev,
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handle_level_irq, "level");
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handle_level_irq, "level");
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irq_set_status_flags(irq, IRQ_LEVEL);
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}
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irq_set_chip_data(irq, irqc);
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return 0;
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}
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@ -138,12 +163,14 @@ static const struct irq_domain_ops xintc_irq_domain_ops = {
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static void xil_intc_irq_handler(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct xintc_irq_chip *irqc;
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u32 pending;
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irqc = irq_data_get_irq_handler_data(&desc->irq_data);
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chained_irq_enter(chip, desc);
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do {
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pending = xintc_get_irq();
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if (pending == -1U)
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pending = xintc_get_irq_local(irqc);
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if (pending == 0)
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break;
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generic_handle_irq(pending);
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} while (true);
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@ -153,28 +180,19 @@ static void xil_intc_irq_handler(struct irq_desc *desc)
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static int __init xilinx_intc_of_init(struct device_node *intc,
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struct device_node *parent)
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{
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u32 nr_irq;
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int ret, irq;
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struct xintc_irq_chip *irqc;
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if (xintc_irqc) {
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pr_err("irq-xilinx: Multiple instances aren't supported\n");
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return -EINVAL;
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}
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int ret, irq;
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irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
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if (!irqc)
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return -ENOMEM;
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xintc_irqc = irqc;
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irqc->base = of_iomap(intc, 0);
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BUG_ON(!irqc->base);
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ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq);
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ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq);
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if (ret < 0) {
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pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");
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goto err_alloc;
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goto error;
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}
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ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);
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@ -183,34 +201,34 @@ static int __init xilinx_intc_of_init(struct device_node *intc,
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irqc->intr_mask = 0;
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}
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if (irqc->intr_mask >> nr_irq)
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if (irqc->intr_mask >> irqc->nr_irq)
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pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
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pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n",
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intc, nr_irq, irqc->intr_mask);
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intc, irqc->nr_irq, irqc->intr_mask);
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/*
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* Disable all external interrupts until they are
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* explicity requested.
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*/
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xintc_write(IER, 0);
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xintc_write(irqc, IER, 0);
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/* Acknowledge any pending interrupts just in case. */
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xintc_write(IAR, 0xffffffff);
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xintc_write(irqc, IAR, 0xffffffff);
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/* Turn on the Master Enable. */
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xintc_write(MER, MER_HIE | MER_ME);
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if (!(xintc_read(MER) & (MER_HIE | MER_ME))) {
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xintc_write(irqc, MER, MER_HIE | MER_ME);
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if (xintc_read(irqc, MER) != (MER_HIE | MER_ME)) {
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static_branch_enable(&xintc_is_be);
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xintc_write(MER, MER_HIE | MER_ME);
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xintc_write(irqc, MER, MER_HIE | MER_ME);
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}
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irqc->root_domain = irq_domain_add_linear(intc, nr_irq,
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irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq,
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&xintc_irq_domain_ops, irqc);
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if (!irqc->root_domain) {
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pr_err("irq-xilinx: Unable to create IRQ domain\n");
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goto err_alloc;
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goto error;
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}
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if (parent) {
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@ -222,16 +240,17 @@ static int __init xilinx_intc_of_init(struct device_node *intc,
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} else {
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pr_err("irq-xilinx: interrupts property not in DT\n");
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ret = -EINVAL;
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goto err_alloc;
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goto error;
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}
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} else {
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irq_set_default_host(irqc->root_domain);
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primary_intc = irqc;
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irq_set_default_host(primary_intc->root_domain);
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}
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return 0;
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err_alloc:
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xintc_irqc = NULL;
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error:
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iounmap(irqc->base);
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kfree(irqc);
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return ret;
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