mirror of https://gitee.com/openkylin/linux.git
drm/i915: extract intel_dp_init_panel_power_sequencer
That thing has grown way too big already. Also move around a comment to the right spot. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
parent
6b3ec1c9fb
commit
67a5456655
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@ -2522,6 +2522,118 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
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intel_attach_broadcast_rgb_property(connector);
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}
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static void
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intel_dp_init_panel_power_sequencer(struct drm_device *dev,
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struct intel_dp *intel_dp)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct edp_power_seq cur, vbt, spec, final;
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u32 pp_on, pp_off, pp_div, pp;
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/* Workaround: Need to write PP_CONTROL with the unlock key as
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* the very first thing. */
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pp = ironlake_get_pp_control(dev_priv);
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I915_WRITE(PCH_PP_CONTROL, pp);
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pp_on = I915_READ(PCH_PP_ON_DELAYS);
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pp_off = I915_READ(PCH_PP_OFF_DELAYS);
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pp_div = I915_READ(PCH_PP_DIVISOR);
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/* Pull timing values out of registers */
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cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
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PANEL_POWER_UP_DELAY_SHIFT;
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cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
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PANEL_LIGHT_ON_DELAY_SHIFT;
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cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
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PANEL_LIGHT_OFF_DELAY_SHIFT;
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cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
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PANEL_POWER_DOWN_DELAY_SHIFT;
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cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
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PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
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DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
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cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
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vbt = dev_priv->edp.pps;
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/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
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* our hw here, which are all in 100usec. */
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spec.t1_t3 = 210 * 10;
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spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
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spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
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spec.t10 = 500 * 10;
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/* This one is special and actually in units of 100ms, but zero
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* based in the hw (so we need to add 100 ms). But the sw vbt
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* table multiplies it with 1000 to make it in units of 100usec,
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* too. */
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spec.t11_t12 = (510 + 100) * 10;
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DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
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vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
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/* Use the max of the register settings and vbt. If both are
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* unset, fall back to the spec limits. */
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#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
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spec.field : \
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max(cur.field, vbt.field))
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assign_final(t1_t3);
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assign_final(t8);
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assign_final(t9);
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assign_final(t10);
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assign_final(t11_t12);
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#undef assign_final
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#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
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intel_dp->panel_power_up_delay = get_delay(t1_t3);
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intel_dp->backlight_on_delay = get_delay(t8);
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intel_dp->backlight_off_delay = get_delay(t9);
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intel_dp->panel_power_down_delay = get_delay(t10);
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intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
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#undef get_delay
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/* And finally store the new values in the power sequencer. */
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pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
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(final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
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pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
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(final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
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/* Compute the divisor for the pp clock, simply match the Bspec
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* formula. */
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pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
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<< PP_REFERENCE_DIVIDER_SHIFT;
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pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
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<< PANEL_POWER_CYCLE_DELAY_SHIFT);
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/* Haswell doesn't have any port selection bits for the panel
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* power sequencer any more. */
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if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
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if (is_cpu_edp(intel_dp))
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pp_on |= PANEL_POWER_PORT_DP_A;
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else
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pp_on |= PANEL_POWER_PORT_DP_D;
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}
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I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
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I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
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I915_WRITE(PCH_PP_DIVISOR, pp_div);
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DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
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intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
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intel_dp->panel_power_cycle_delay);
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DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
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intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
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DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
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I915_READ(PCH_PP_ON_DELAYS),
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I915_READ(PCH_PP_OFF_DELAYS),
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I915_READ(PCH_PP_DIVISOR));
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}
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void
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intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
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{
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@ -2636,117 +2748,12 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
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break;
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}
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/* Cache some DPCD data in the eDP case */
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if (is_edp(intel_dp)) {
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struct edp_power_seq cur, vbt, spec, final;
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u32 pp_on, pp_off, pp_div, pp;
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/* Workaround: Need to write PP_CONTROL with the unlock key as
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* the very first thing. */
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pp = ironlake_get_pp_control(dev_priv);
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I915_WRITE(PCH_PP_CONTROL, pp);
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pp_on = I915_READ(PCH_PP_ON_DELAYS);
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pp_off = I915_READ(PCH_PP_OFF_DELAYS);
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pp_div = I915_READ(PCH_PP_DIVISOR);
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/* Pull timing values out of registers */
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cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
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PANEL_POWER_UP_DELAY_SHIFT;
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cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
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PANEL_LIGHT_ON_DELAY_SHIFT;
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cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
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PANEL_LIGHT_OFF_DELAY_SHIFT;
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cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
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PANEL_POWER_DOWN_DELAY_SHIFT;
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cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
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PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
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DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
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cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
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vbt = dev_priv->edp.pps;
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/* Upper limits from eDP 1.3 spec. Note that we use the clunky
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* units of our hw here, which are all in 100usec. */
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spec.t1_t3 = 210 * 10;
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spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
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spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
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spec.t10 = 500 * 10;
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/* This one is special and actually in units of 100ms, but zero
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* based in the hw (so we need to add 100 ms). But the sw vbt
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* table multiplies it with 1000 to make it in units of 100usec,
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* too. */
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spec.t11_t12 = (510 + 100) * 10;
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DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
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vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
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/* Use the max of the register settings and vbt. If both are
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* unset, fall back to the spec limits. */
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#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
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spec.field : \
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max(cur.field, vbt.field))
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assign_final(t1_t3);
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assign_final(t8);
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assign_final(t9);
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assign_final(t10);
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assign_final(t11_t12);
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#undef assign_final
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#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
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intel_dp->panel_power_up_delay = get_delay(t1_t3);
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intel_dp->backlight_on_delay = get_delay(t8);
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intel_dp->backlight_off_delay = get_delay(t9);
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intel_dp->panel_power_down_delay = get_delay(t10);
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intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
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#undef get_delay
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/* And finally store the new values in the power sequencer. */
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pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
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(final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
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pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
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(final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
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/* Compute the divisor for the pp clock, simply match the Bspec
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* formula. */
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pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
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<< PP_REFERENCE_DIVIDER_SHIFT;
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pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
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<< PANEL_POWER_CYCLE_DELAY_SHIFT);
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/* Haswell doesn't have any port selection bits for the panel
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* power sequence any more. */
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if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
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if (is_cpu_edp(intel_dp))
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pp_on |= PANEL_POWER_PORT_DP_A;
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else
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pp_on |= PANEL_POWER_PORT_DP_D;
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}
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I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
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I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
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I915_WRITE(PCH_PP_DIVISOR, pp_div);
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DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
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intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
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intel_dp->panel_power_cycle_delay);
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DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
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intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
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DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
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I915_READ(PCH_PP_ON_DELAYS),
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I915_READ(PCH_PP_OFF_DELAYS),
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I915_READ(PCH_PP_DIVISOR));
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}
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if (is_edp(intel_dp))
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intel_dp_init_panel_power_sequencer(dev, intel_dp);
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intel_dp_i2c_init(intel_dp, intel_connector, name);
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/* Cache DPCD and EDID for edp. */
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if (is_edp(intel_dp)) {
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bool ret;
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struct drm_display_mode *scan;
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