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ARM: dts: apq8064: fix the pinctrls for i2c and spi 

This patch fixes pinctrls for spi and i2c nodes whose default and sleep
states are together, which is incorrect.

Without this patch i2c/spi would not be functional.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Srinivas Kandagatla 2016-04-12 10:33:50 +01:00 committed by Andy Gross
parent 2afc5287c5
commit 67b5ad57df
1 changed files with 12 additions and 6 deletions
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18
arch/arm/boot/dts/qcom-apq8064.dtsi
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@ -321,7 +321,8 @@ gsbi1: gsbi@12440000 {
gsbi1_i2c: i2c@12460000 { gsbi1_i2c: i2c@12460000 {
compatible = "qcom,i2c-qup-v1.1.1"; compatible = "qcom,i2c-qup-v1.1.1";
pinctrl-0 = <&i2c1_pins &i2c1_pins_sleep>; pinctrl-0 = <&i2c1_pins>;
pinctrl-1 = <&i2c1_pins_sleep>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
reg = <0x12460000 0x1000>; reg = <0x12460000 0x1000>;
interrupts = <0 194 IRQ_TYPE_NONE>; interrupts = <0 194 IRQ_TYPE_NONE>;
@ -349,7 +350,8 @@ gsbi2: gsbi@12480000 {
gsbi2_i2c: i2c@124a0000 { gsbi2_i2c: i2c@124a0000 {
compatible = "qcom,i2c-qup-v1.1.1"; compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x124a0000 0x1000>; reg = <0x124a0000 0x1000>;
pinctrl-0 = <&i2c2_pins &i2c2_pins_sleep>; pinctrl-0 = <&i2c2_pins>;
pinctrl-1 = <&i2c2_pins_sleep>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
interrupts = <0 196 IRQ_TYPE_NONE>; interrupts = <0 196 IRQ_TYPE_NONE>;
clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
@ -371,7 +373,8 @@ gsbi3: gsbi@16200000 {
ranges; ranges;
gsbi3_i2c: i2c@16280000 { gsbi3_i2c: i2c@16280000 {
compatible = "qcom,i2c-qup-v1.1.1"; compatible = "qcom,i2c-qup-v1.1.1";
pinctrl-0 = <&i2c3_pins &i2c3_pins_sleep>; pinctrl-0 = <&i2c3_pins>;
pinctrl-1 = <&i2c3_pins_sleep>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
reg = <0x16280000 0x1000>; reg = <0x16280000 0x1000>;
interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
@ -396,7 +399,8 @@ gsbi4: gsbi@16300000 {
gsbi4_i2c: i2c@16380000 { gsbi4_i2c: i2c@16380000 {
compatible = "qcom,i2c-qup-v1.1.1"; compatible = "qcom,i2c-qup-v1.1.1";
pinctrl-0 = <&i2c4_pins &i2c4_pins_sleep>; pinctrl-0 = <&i2c4_pins>;
pinctrl-1 = <&i2c4_pins_sleep>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
reg = <0x16380000 0x1000>; reg = <0x16380000 0x1000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>; interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
@ -431,7 +435,8 @@ gsbi5_spi: spi@1a280000 {
compatible = "qcom,spi-qup-v1.1.1"; compatible = "qcom,spi-qup-v1.1.1";
reg = <0x1a280000 0x1000>; reg = <0x1a280000 0x1000>;
interrupts = <0 155 0>; interrupts = <0 155 0>;
pinctrl-0 = <&spi5_default &spi5_sleep>; pinctrl-0 = <&spi5_default>;
pinctrl-1 = <&spi5_sleep>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface"; clock-names = "core", "iface";
@ -464,7 +469,8 @@ gsbi6_serial: serial@16540000 {
gsbi6_i2c: i2c@16580000 { gsbi6_i2c: i2c@16580000 {
compatible = "qcom,i2c-qup-v1.1.1"; compatible = "qcom,i2c-qup-v1.1.1";
pinctrl-0 = <&i2c6_pins &i2c6_pins_sleep>; pinctrl-0 = <&i2c6_pins>;
pinctrl-1 = <&i2c6_pins_sleep>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
reg = <0x16580000 0x1000>; reg = <0x16580000 0x1000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;