mirror of https://gitee.com/openkylin/linux.git
dmaengine: sun6i: Add a quirk for setting DRQ fields
H6 DMA has more than 32 possible DRQs. That means that current maximum of 31 DRQs is not enough anymore. Add a quirk which will set source and destination DRQ number. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Clément Péron <peron.clem@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Jernej Skrabec
Vinod Koul
parent
43a90fc76a
commit
67f3405511
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@ -68,15 +68,15 @@
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#define DMA_CHAN_LLI_ADDR 0x08
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#define DMA_CHAN_CUR_CFG 0x0c
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#define DMA_CHAN_MAX_DRQ 0x1f
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#define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & DMA_CHAN_MAX_DRQ)
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#define DMA_CHAN_MAX_DRQ_A31 0x1f
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#define DMA_CHAN_CFG_SRC_DRQ_A31(x) ((x) & DMA_CHAN_MAX_DRQ_A31)
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#define DMA_CHAN_CFG_SRC_IO_MODE BIT(5)
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#define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5)
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#define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7)
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#define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6)
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#define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9)
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#define DMA_CHAN_CFG_DST_DRQ(x) (DMA_CHAN_CFG_SRC_DRQ(x) << 16)
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#define DMA_CHAN_CFG_DST_DRQ_A31(x) (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16)
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#define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16)
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#define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16)
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#define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)
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@ -125,6 +125,7 @@ struct sun6i_dma_config {
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*/
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void (*clock_autogate_enable)(struct sun6i_dma_dev *);
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void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst);
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void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq);
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u32 src_burst_lengths;
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u32 dst_burst_lengths;
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u32 src_addr_widths;
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@ -311,6 +312,12 @@ static void sun6i_set_burst_length_h3(u32 *p_cfg, s8 src_burst, s8 dst_burst)
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DMA_CHAN_CFG_DST_BURST_H3(dst_burst);
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}
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static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq)
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{
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*p_cfg |= DMA_CHAN_CFG_SRC_DRQ_A31(src_drq) |
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DMA_CHAN_CFG_DST_DRQ_A31(dst_drq);
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}
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static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)
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{
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struct sun6i_desc *txd = pchan->desc;
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@ -634,14 +641,13 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
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burst = convert_burst(8);
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width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);
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v_lli->cfg = DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
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DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
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DMA_CHAN_CFG_DST_LINEAR_MODE |
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v_lli->cfg = DMA_CHAN_CFG_DST_LINEAR_MODE |
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DMA_CHAN_CFG_SRC_LINEAR_MODE |
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DMA_CHAN_CFG_SRC_WIDTH(width) |
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DMA_CHAN_CFG_DST_WIDTH(width);
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sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst);
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sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, DRQ_SDRAM);
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sun6i_dma_lli_add(NULL, v_lli, p_lli, txd);
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@ -695,9 +701,8 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
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v_lli->dst = sconfig->dst_addr;
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v_lli->cfg = lli_cfg |
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DMA_CHAN_CFG_DST_IO_MODE |
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DMA_CHAN_CFG_SRC_LINEAR_MODE |
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DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
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DMA_CHAN_CFG_DST_DRQ(vchan->port);
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DMA_CHAN_CFG_SRC_LINEAR_MODE;
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sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
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dev_dbg(chan2dev(chan),
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"%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
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@ -710,9 +715,8 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
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v_lli->dst = sg_dma_address(sg);
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v_lli->cfg = lli_cfg |
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DMA_CHAN_CFG_DST_LINEAR_MODE |
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DMA_CHAN_CFG_SRC_IO_MODE |
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DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
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DMA_CHAN_CFG_SRC_DRQ(vchan->port);
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DMA_CHAN_CFG_SRC_IO_MODE;
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sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
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dev_dbg(chan2dev(chan),
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"%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
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@ -780,17 +784,15 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic(
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v_lli->dst = sconfig->dst_addr;
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v_lli->cfg = lli_cfg |
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DMA_CHAN_CFG_DST_IO_MODE |
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DMA_CHAN_CFG_SRC_LINEAR_MODE |
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DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
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DMA_CHAN_CFG_DST_DRQ(vchan->port);
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DMA_CHAN_CFG_SRC_LINEAR_MODE;
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sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
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} else {
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v_lli->src = sconfig->src_addr;
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v_lli->dst = buf_addr + period_len * i;
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v_lli->cfg = lli_cfg |
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DMA_CHAN_CFG_DST_LINEAR_MODE |
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DMA_CHAN_CFG_SRC_IO_MODE |
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DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
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DMA_CHAN_CFG_SRC_DRQ(vchan->port);
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DMA_CHAN_CFG_SRC_IO_MODE;
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sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
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}
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prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
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@ -1055,6 +1057,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = {
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.nr_max_requests = 30,
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.nr_max_vchans = 53,
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.set_burst_length = sun6i_set_burst_length_a31,
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.set_drq = sun6i_set_drq_a31,
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.src_burst_lengths = BIT(1) | BIT(8),
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.dst_burst_lengths = BIT(1) | BIT(8),
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.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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@ -1076,6 +1079,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = {
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.nr_max_vchans = 37,
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.clock_autogate_enable = sun6i_enable_clock_autogate_a23,
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.set_burst_length = sun6i_set_burst_length_a31,
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.set_drq = sun6i_set_drq_a31,
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.src_burst_lengths = BIT(1) | BIT(8),
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.dst_burst_lengths = BIT(1) | BIT(8),
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.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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@ -1092,6 +1096,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = {
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.nr_max_vchans = 39,
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.clock_autogate_enable = sun6i_enable_clock_autogate_a23,
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.set_burst_length = sun6i_set_burst_length_a31,
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.set_drq = sun6i_set_drq_a31,
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.src_burst_lengths = BIT(1) | BIT(8),
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.dst_burst_lengths = BIT(1) | BIT(8),
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.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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@ -1115,6 +1120,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
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.nr_max_vchans = 34,
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.clock_autogate_enable = sun6i_enable_clock_autogate_h3,
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.set_burst_length = sun6i_set_burst_length_h3,
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.set_drq = sun6i_set_drq_a31,
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.src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
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.dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
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.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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@ -1134,6 +1140,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
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static struct sun6i_dma_config sun50i_a64_dma_cfg = {
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.clock_autogate_enable = sun6i_enable_clock_autogate_h3,
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.set_burst_length = sun6i_set_burst_length_h3,
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.set_drq = sun6i_set_drq_a31,
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.src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
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.dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
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.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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@ -1157,6 +1164,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = {
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.nr_max_vchans = 24,
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.clock_autogate_enable = sun6i_enable_clock_autogate_a23,
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.set_burst_length = sun6i_set_burst_length_a31,
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.set_drq = sun6i_set_drq_a31,
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.src_burst_lengths = BIT(1) | BIT(8),
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.dst_burst_lengths = BIT(1) | BIT(8),
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.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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@ -1272,8 +1280,8 @@ static int sun6i_dma_probe(struct platform_device *pdev)
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ret = of_property_read_u32(np, "dma-requests", &sdc->max_request);
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if (ret && !sdc->max_request) {
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dev_info(&pdev->dev, "Missing dma-requests, using %u.\n",
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DMA_CHAN_MAX_DRQ);
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sdc->max_request = DMA_CHAN_MAX_DRQ;
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DMA_CHAN_MAX_DRQ_A31);
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sdc->max_request = DMA_CHAN_MAX_DRQ_A31;
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}
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/*
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