mirror of https://gitee.com/openkylin/linux.git
Amlogic SoC updates for v4.15
- add SMP support to Meson8/8b -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAln2AfgACgkQWTcYmtP7 xmXP+A//U3cBORd3lkmaVxGzcul/IB0czVH1XJp+WgMi2ksuin3UjveANFFxIUtL cqBBNV23+PDjgFZF+SAbuEMIyWKoxvuxJ6ktKoP3N9MQsyb2yM9t2ITDfGCcHQ/E xu5vjuYDqfjpowLcDE2yFTZbDV980gc7QyJvhwX9Bcxod+KfXz7C60J57qxRar0C F5ViskncTvka3NlQGcCvZz0Wd1J5rMcBncmWpqQPKTyKg22gqbYgISHOWay6h6G4 otNhcnN4FeVgem9v/k1BUe6edIO9CQrhIITFdnT6B6NxmpQ2rFvK/hwboqOFRoL/ 6v8nHtV3SIkxHiT06slkNeXvLKDGBr/3pFzswz/pPDXKiIJpeVbwFrFBv6L6V2Bz P0MdbRFEO8KODud8Z+ZTl3Gwqlv/8ISb18dOuxaPtK/cbNzffrmZqwvNe6IfkVGW zQrxnknxoLHb07lQ1lRHQiwHvmOdlK5l/9VVVE07fRUbIvR05JdX0KhU/1rs3dPv Gsu25nb5Jn59rWTlRzw0O9P5ER/AMObfjsMMhF/Fj8bzcLGSJVhrNXGtWQ/+D20I zsDJOfoWiwIa1ezoY7S8nIj0sNz5Xp14+MMOw2Wz0L1lXGla9qJsUNQANlI933Uz zXwDSGLEhLkaNwvOXLXNVPnnTkenNeDPPeaBJ7FuJo5o/1UxQOs= =1tXJ -----END PGP SIGNATURE----- Merge tag 'amlogic-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/soc Pull "Amlogic SoC updates for v4.15" from Kevin Hilman: - add SMP support to Meson8/8b * tag 'amlogic-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM: meson: enable MESON_IRQ_GPIO in Kconfig for meson8b ARM: meson: Add SMP bringup code for Meson8 and Meson8b ARM: smp_scu: allow the platform code to read the SCU CPU status ARM: smp_scu: add a helper for powering on a specific CPU dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation
This commit is contained in:
Arnd Bergmann
commit
682e3efa4d
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@ -0,0 +1,18 @@
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Amlogic Meson8 and Meson8b power-management-unit:
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-------------------------------------------------
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The pmu is used to turn off and on different power domains of the SoCs
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This includes the power to the CPU cores.
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Required node properties:
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- compatible value : depending on the SoC this should be one of:
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"amlogic,meson8-pmu"
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"amlogic,meson8b-pmu"
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- reg : physical base address and the size of the registers window
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Example:
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pmu@c81000e4 {
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compatible = "amlogic,meson8b-pmu", "syscon";
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reg = <0xc81000e0 0x18>;
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};
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@ -0,0 +1,32 @@
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Amlogic Meson8 and Meson8b SRAM for smp bringup:
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------------------------------------------------
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Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
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Once the core gets powered up it executes the code that is residing at a
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specific location.
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Therefore a reserved section sub-node has to be added to the mmio-sram
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declaration.
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Required sub-node properties:
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- compatible : depending on the SoC this should be one of:
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"amlogic,meson8-smp-sram"
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"amlogic,meson8b-smp-sram"
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The rest of the properties should follow the generic mmio-sram discription
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found in ../../misc/sram.txt
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Example:
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sram: sram@d9000000 {
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compatible = "mmio-sram";
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reg = <0xd9000000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xd9000000 0x20000>;
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smp-sram@1ff80 {
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compatible = "amlogic,meson8b-smp-sram";
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reg = <0x1ff80 0x8>;
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};
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};
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@ -197,6 +197,8 @@ described below.
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"actions,s500-smp"
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"allwinner,sun6i-a31"
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"allwinner,sun8i-a23"
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"amlogic,meson8-smp"
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"amlogic,meson8b-smp"
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"arm,realview-smp"
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"brcm,bcm11351-cpu-method"
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"brcm,bcm23550"
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@ -147,6 +147,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
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endif
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textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
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textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
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textofs-$(CONFIG_ARCH_MESON) := 0x00208000
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textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
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# Machine directory name. This list is sorted alphanumerically
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@ -27,6 +27,8 @@ static inline unsigned long scu_a9_get_base(void)
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#ifdef CONFIG_HAVE_ARM_SCU
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unsigned int scu_get_core_count(void __iomem *);
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int scu_power_mode(void __iomem *, unsigned int);
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int scu_cpu_power_enable(void __iomem *, unsigned int);
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int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu);
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#else
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static inline unsigned int scu_get_core_count(void __iomem *scu_base)
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{
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@ -36,6 +38,16 @@ static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode)
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{
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return -EINVAL;
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}
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static inline int scu_cpu_power_enable(void __iomem *scu_base,
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unsigned int mode)
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{
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return -EINVAL;
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}
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static inline int scu_get_cpu_power_mode(void __iomem *scu_base,
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unsigned int logical_cpu)
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{
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return -EINVAL;
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}
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#endif
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#if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)
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@ -21,6 +21,7 @@
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#define SCU_STANDBY_ENABLE (1 << 5)
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#define SCU_CONFIG 0x04
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#define SCU_CPU_STATUS 0x08
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#define SCU_CPU_STATUS_MASK GENMASK(1, 0)
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#define SCU_INVALIDATE 0x0c
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#define SCU_FPGA_REVISION 0x10
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@ -72,6 +73,24 @@ void scu_enable(void __iomem *scu_base)
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}
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#endif
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static int scu_set_power_mode_internal(void __iomem *scu_base,
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unsigned int logical_cpu,
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unsigned int mode)
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{
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unsigned int val;
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int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);
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if (mode > 3 || mode == 1 || cpu > 3)
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return -EINVAL;
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val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
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val &= ~SCU_CPU_STATUS_MASK;
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val |= mode;
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writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
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return 0;
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}
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/*
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* Set the executing CPUs power mode as defined. This will be in
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* preparation for it executing a WFI instruction.
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@ -82,15 +101,27 @@ void scu_enable(void __iomem *scu_base)
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*/
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int scu_power_mode(void __iomem *scu_base, unsigned int mode)
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{
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unsigned int val;
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int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
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return scu_set_power_mode_internal(scu_base, smp_processor_id(), mode);
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}
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if (mode > 3 || mode == 1 || cpu > 3)
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/*
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* Set the given (logical) CPU's power mode to SCU_PM_NORMAL.
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*/
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int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu)
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{
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return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL);
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}
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int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu)
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{
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unsigned int val;
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int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);
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if (cpu > 3)
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return -EINVAL;
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val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
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val |= mode;
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writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
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val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
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val &= SCU_CPU_STATUS_MASK;
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return 0;
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return val;
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}
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@ -9,6 +9,7 @@ menuconfig ARCH_MESON
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select PINCTRL_MESON
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select COMMON_CLK
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select COMMON_CLK_AMLOGIC
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select HAVE_ARM_SCU if SMP
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if ARCH_MESON
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@ -28,5 +29,6 @@ config MACH_MESON8B
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default ARCH_MESON
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select MESON6_TIMER
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select COMMON_CLK_MESON8B
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select MESON_IRQ_GPIO
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endif
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@ -1 +1,2 @@
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obj-$(CONFIG_ARCH_MESON) += meson.o
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obj-$(CONFIG_SMP) += platsmp.o
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@ -0,0 +1,440 @@
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/*
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* Copyright (C) 2015 Carlo Caione <carlo@endlessm.com>
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* Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/smp.h>
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#include <linux/mfd/syscon.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_plat.h>
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#define MESON_SMP_SRAM_CPU_CTRL_REG (0x00)
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#define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2))
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#define MESON_CPU_AO_RTI_PWR_A9_CNTL0 (0x00)
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#define MESON_CPU_AO_RTI_PWR_A9_CNTL1 (0x04)
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#define MESON_CPU_AO_RTI_PWR_A9_MEM_PD0 (0x14)
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#define MESON_CPU_PWR_A9_CNTL0_M(c) (0x03 << ((c * 2) + 16))
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#define MESON_CPU_PWR_A9_CNTL1_M(c) (0x03 << ((c + 1) << 1))
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#define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4)))
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#define MESON_CPU_PWR_A9_CNTL1_ST(c) (0x01 << (c + 16))
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static void __iomem *sram_base;
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static void __iomem *scu_base;
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static struct regmap *pmu;
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static struct reset_control *meson_smp_get_core_reset(int cpu)
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{
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struct device_node *np = of_get_cpu_node(cpu, 0);
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return of_reset_control_get_exclusive(np, NULL);
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}
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static void meson_smp_set_cpu_ctrl(int cpu, bool on_off)
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{
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u32 val = readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
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if (on_off)
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val |= BIT(cpu);
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else
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val &= ~BIT(cpu);
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/* keep bit 0 always enabled */
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val |= BIT(0);
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writel(val, sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
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}
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static void __init meson_smp_prepare_cpus(const char *scu_compatible,
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const char *pmu_compatible,
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const char *sram_compatible)
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{
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static struct device_node *node;
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/* SMP SRAM */
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node = of_find_compatible_node(NULL, NULL, sram_compatible);
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if (!node) {
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pr_err("Missing SRAM node\n");
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return;
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}
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sram_base = of_iomap(node, 0);
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if (!sram_base) {
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pr_err("Couldn't map SRAM registers\n");
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return;
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}
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/* PMU */
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pmu = syscon_regmap_lookup_by_compatible(pmu_compatible);
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if (IS_ERR(pmu)) {
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pr_err("Couldn't map PMU registers\n");
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return;
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}
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/* SCU */
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node = of_find_compatible_node(NULL, NULL, scu_compatible);
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if (!node) {
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pr_err("Missing SCU node\n");
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return;
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}
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scu_base = of_iomap(node, 0);
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if (!scu_base) {
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pr_err("Couln't map SCU registers\n");
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return;
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}
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scu_enable(scu_base);
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}
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static void __init meson8b_smp_prepare_cpus(unsigned int max_cpus)
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{
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meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu",
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"amlogic,meson8b-smp-sram");
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}
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static void __init meson8_smp_prepare_cpus(unsigned int max_cpus)
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{
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meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu",
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"amlogic,meson8-smp-sram");
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}
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static void meson_smp_begin_secondary_boot(unsigned int cpu)
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{
|
||||
/*
|
||||
* Set the entry point before powering on the CPU through the SCU. This
|
||||
* is needed if the CPU is in "warm" state (= after rebooting the
|
||||
* system without power-cycling, or when taking the CPU offline and
|
||||
* then taking it online again.
|
||||
*/
|
||||
writel(__pa_symbol(secondary_startup),
|
||||
sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));
|
||||
|
||||
/*
|
||||
* SCU Power on CPU (needs to be done before starting the CPU,
|
||||
* otherwise the secondary CPU will not start).
|
||||
*/
|
||||
scu_cpu_power_enable(scu_base, cpu);
|
||||
}
|
||||
|
||||
static int meson_smp_finalize_secondary_boot(unsigned int cpu)
|
||||
{
|
||||
unsigned long timeout;
|
||||
|
||||
timeout = jiffies + (10 * HZ);
|
||||
while (readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu))) {
|
||||
if (!time_before(jiffies, timeout)) {
|
||||
pr_err("Timeout while waiting for CPU%d status\n",
|
||||
cpu);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
writel(__pa_symbol(secondary_startup),
|
||||
sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));
|
||||
|
||||
meson_smp_set_cpu_ctrl(cpu, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson8_smp_boot_secondary(unsigned int cpu,
|
||||
struct task_struct *idle)
|
||||
{
|
||||
struct reset_control *rstc;
|
||||
int ret;
|
||||
|
||||
rstc = meson_smp_get_core_reset(cpu);
|
||||
if (IS_ERR(rstc)) {
|
||||
pr_err("Couldn't get the reset controller for CPU%d\n", cpu);
|
||||
return PTR_ERR(rstc);
|
||||
}
|
||||
|
||||
meson_smp_begin_secondary_boot(cpu);
|
||||
|
||||
/* Reset enable */
|
||||
ret = reset_control_assert(rstc);
|
||||
if (ret) {
|
||||
pr_err("Failed to assert CPU%d reset\n", cpu);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* CPU power ON */
|
||||
ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
|
||||
MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
|
||||
if (ret < 0) {
|
||||
pr_err("Couldn't wake up CPU%d\n", cpu);
|
||||
goto out;
|
||||
}
|
||||
|
||||
udelay(10);
|
||||
|
||||
/* Isolation disable */
|
||||
ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
|
||||
0);
|
||||
if (ret < 0) {
|
||||
pr_err("Error when disabling isolation of CPU%d\n", cpu);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Reset disable */
|
||||
ret = reset_control_deassert(rstc);
|
||||
if (ret) {
|
||||
pr_err("Failed to de-assert CPU%d reset\n", cpu);
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = meson_smp_finalize_secondary_boot(cpu);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
out:
|
||||
reset_control_put(rstc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson8b_smp_boot_secondary(unsigned int cpu,
|
||||
struct task_struct *idle)
|
||||
{
|
||||
struct reset_control *rstc;
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
rstc = meson_smp_get_core_reset(cpu);
|
||||
if (IS_ERR(rstc)) {
|
||||
pr_err("Couldn't get the reset controller for CPU%d\n", cpu);
|
||||
return PTR_ERR(rstc);
|
||||
}
|
||||
|
||||
meson_smp_begin_secondary_boot(cpu);
|
||||
|
||||
/* CPU power UP */
|
||||
ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
|
||||
MESON_CPU_PWR_A9_CNTL0_M(cpu), 0);
|
||||
if (ret < 0) {
|
||||
pr_err("Couldn't power up CPU%d\n", cpu);
|
||||
goto out;
|
||||
}
|
||||
|
||||
udelay(5);
|
||||
|
||||
/* Reset enable */
|
||||
ret = reset_control_assert(rstc);
|
||||
if (ret) {
|
||||
pr_err("Failed to assert CPU%d reset\n", cpu);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Memory power UP */
|
||||
ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
|
||||
MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0);
|
||||
if (ret < 0) {
|
||||
pr_err("Couldn't power up the memory for CPU%d\n", cpu);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Wake up CPU */
|
||||
ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
|
||||
MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
|
||||
if (ret < 0) {
|
||||
pr_err("Couldn't wake up CPU%d\n", cpu);
|
||||
goto out;
|
||||
}
|
||||
|
||||
udelay(10);
|
||||
|
||||
ret = regmap_read_poll_timeout(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, val,
|
||||
val & MESON_CPU_PWR_A9_CNTL1_ST(cpu),
|
||||
10, 10000);
|
||||
if (ret) {
|
||||
pr_err("Timeout while polling PMU for CPU%d status\n", cpu);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Isolation disable */
|
||||
ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
|
||||
0);
|
||||
if (ret < 0) {
|
||||
pr_err("Error when disabling isolation of CPU%d\n", cpu);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Reset disable */
|
||||
ret = reset_control_deassert(rstc);
|
||||
if (ret) {
|
||||
pr_err("Failed to de-assert CPU%d reset\n", cpu);
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = meson_smp_finalize_secondary_boot(cpu);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
out:
|
||||
reset_control_put(rstc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
static void meson8_smp_cpu_die(unsigned int cpu)
|
||||
{
|
||||
meson_smp_set_cpu_ctrl(cpu, false);
|
||||
|
||||
v7_exit_coherency_flush(louis);
|
||||
|
||||
scu_power_mode(scu_base, SCU_PM_POWEROFF);
|
||||
|
||||
dsb();
|
||||
wfi();
|
||||
|
||||
/* we should never get here */
|
||||
WARN_ON(1);
|
||||
}
|
||||
|
||||
static int meson8_smp_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
int ret, power_mode;
|
||||
unsigned long timeout;
|
||||
|
||||
timeout = jiffies + (50 * HZ);
|
||||
do {
|
||||
power_mode = scu_get_cpu_power_mode(scu_base, cpu);
|
||||
|
||||
if (power_mode == SCU_PM_POWEROFF)
|
||||
break;
|
||||
|
||||
usleep_range(10000, 15000);
|
||||
} while (time_before(jiffies, timeout));
|
||||
|
||||
if (power_mode != SCU_PM_POWEROFF) {
|
||||
pr_err("Error while waiting for SCU power-off on CPU%d\n",
|
||||
cpu);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
msleep(30);
|
||||
|
||||
/* Isolation enable */
|
||||
ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
|
||||
0x3);
|
||||
if (ret < 0) {
|
||||
pr_err("Error when enabling isolation for CPU%d\n", cpu);
|
||||
return ret;
|
||||
}
|
||||
|
||||
udelay(10);
|
||||
|
||||
/* CPU power OFF */
|
||||
ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
|
||||
MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
|
||||
if (ret < 0) {
|
||||
pr_err("Couldn't change sleep status of CPU%d\n", cpu);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int meson8b_smp_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
int ret, power_mode, count = 5000;
|
||||
|
||||
do {
|
||||
power_mode = scu_get_cpu_power_mode(scu_base, cpu);
|
||||
|
||||
if (power_mode == SCU_PM_POWEROFF)
|
||||
break;
|
||||
|
||||
udelay(10);
|
||||
} while (++count);
|
||||
|
||||
if (power_mode != SCU_PM_POWEROFF) {
|
||||
pr_err("Error while waiting for SCU power-off on CPU%d\n",
|
||||
cpu);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
udelay(10);
|
||||
|
||||
/* CPU power DOWN */
|
||||
ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
|
||||
MESON_CPU_PWR_A9_CNTL0_M(cpu), 0x3);
|
||||
if (ret < 0) {
|
||||
pr_err("Couldn't power down CPU%d\n", cpu);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Isolation enable */
|
||||
ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
|
||||
0x3);
|
||||
if (ret < 0) {
|
||||
pr_err("Error when enabling isolation for CPU%d\n", cpu);
|
||||
return ret;
|
||||
}
|
||||
|
||||
udelay(10);
|
||||
|
||||
/* Sleep status */
|
||||
ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
|
||||
MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
|
||||
if (ret < 0) {
|
||||
pr_err("Couldn't change sleep status of CPU%d\n", cpu);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Memory power DOWN */
|
||||
ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
|
||||
MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0xf);
|
||||
if (ret < 0) {
|
||||
pr_err("Couldn't power down the memory of CPU%d\n", cpu);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct smp_operations meson8_smp_ops __initdata = {
|
||||
.smp_prepare_cpus = meson8_smp_prepare_cpus,
|
||||
.smp_boot_secondary = meson8_smp_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_die = meson8_smp_cpu_die,
|
||||
.cpu_kill = meson8_smp_cpu_kill,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct smp_operations meson8b_smp_ops __initdata = {
|
||||
.smp_prepare_cpus = meson8b_smp_prepare_cpus,
|
||||
.smp_boot_secondary = meson8b_smp_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_die = meson8_smp_cpu_die,
|
||||
.cpu_kill = meson8b_smp_cpu_kill,
|
||||
#endif
|
||||
};
|
||||
|
||||
CPU_METHOD_OF_DECLARE(meson8_smp, "amlogic,meson8-smp", &meson8_smp_ops);
|
||||
CPU_METHOD_OF_DECLARE(meson8b_smp, "amlogic,meson8b-smp", &meson8b_smp_ops);
|
||||
Loading…
Reference in New Issue