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ARM: dts: imx6: Add unit address and reg for the anatop nodes 

Add unit address and reg for the anatop nodes in order to fix the
following build warnings with W=1:

arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@2000000/anatop@20c8000/regulator-1p1 missing or empty reg/ranges property
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@2000000/anatop@20c8000/regulator-3p0 missing or empty reg/ranges property
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@2000000/anatop@20c8000/regulator-2p5 missing or empty reg/ranges property
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddcore missing or empty reg/ranges property
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddpu missing or empty reg/ranges property
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddsoc missing or empty reg/ranges property

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Fabio Estevam 2017-11-29 16:54:36 -02:00 committed by Shawn Guo
parent 1e98960372
commit 685e1321ba
4 changed files with 50 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -695,8 +695,11 @@ anatop: anatop@20c8000 {
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
regulator-1p1 {
regulator-1p1@20c8110 {
reg = <0x20c8110>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <1000000>;
@ -711,7 +714,8 @@ regulator-1p1 {
anatop-enable-bit = <0>;
};
regulator-3p0 {
regulator-3p0@20c8120 {
reg = <0x20c8120>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
@ -726,7 +730,8 @@ regulator-3p0 {
anatop-enable-bit = <0>;
};
regulator-2p5 {
regulator-2p5@20c8130 {
reg = <0x20c8130>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2250000>;
@ -741,7 +746,8 @@ regulator-2p5 {
anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
reg_arm: regulator-vddcore@20c8140 {
reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddarm";
regulator-min-microvolt = <725000>;
@ -758,7 +764,8 @@ reg_arm: regulator-vddcore {
anatop-max-voltage = <1450000>;
};
reg_pu: regulator-vddpu {
reg_pu: regulator-vddpu@20c8140 {
reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
@ -775,7 +782,8 @@ reg_pu: regulator-vddpu {
anatop-max-voltage = <1450000>;
};
reg_soc: regulator-vddsoc {
reg_soc: regulator-vddsoc@20c8140 {
reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;

20
arch/arm/boot/dts/imx6sl.dtsi
View File

@ -527,8 +527,11 @@ anatop: anatop@20c8000 {
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
regulator-1p1 {
regulator-1p1@20c8110 {
reg = <0x20c8110>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <800000>;
@ -543,7 +546,8 @@ regulator-1p1 {
anatop-enable-bit = <0>;
};
regulator-3p0 {
regulator-3p0@20c8120 {
reg = <0x20c8120>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
@ -558,7 +562,8 @@ regulator-3p0 {
anatop-enable-bit = <0>;
};
regulator-2p5 {
regulator-2p5@20c8130 {
reg = <0x20c8130>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2100000>;
@ -573,7 +578,8 @@ regulator-2p5 {
anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
reg_arm: regulator-vddcore@20c8140 {
reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddarm";
regulator-min-microvolt = <725000>;
@ -590,7 +596,8 @@ reg_arm: regulator-vddcore {
anatop-max-voltage = <1450000>;
};
reg_pu: regulator-vddpu {
reg_pu: regulator-vddpu@20c8140 {
reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
@ -607,7 +614,8 @@ reg_pu: regulator-vddpu {
anatop-max-voltage = <1450000>;
};
reg_soc: regulator-vddsoc {
reg_soc: regulator-vddsoc@20c8140 {
reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;

20
arch/arm/boot/dts/imx6sx.dtsi
View File

@ -585,8 +585,11 @@ anatop: anatop@20c8000 {
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
regulator-1p1 {
regulator-1p1@20c8110 {
reg = <0x20c8110>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <800000>;
@ -601,7 +604,8 @@ regulator-1p1 {
anatop-enable-bit = <0>;
};
regulator-3p0 {
regulator-3p0@20c8120 {
reg = <0x20c8120>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
@ -616,7 +620,8 @@ regulator-3p0 {
anatop-enable-bit = <0>;
};
regulator-2p5 {
regulator-2p5@20c8130 {
reg = <0x20c8130>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2100000>;
@ -631,7 +636,8 @@ regulator-2p5 {
anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
reg_arm: regulator-vddcore@20c8140 {
reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddarm";
regulator-min-microvolt = <725000>;
@ -648,7 +654,8 @@ reg_arm: regulator-vddcore {
anatop-max-voltage = <1450000>;
};
reg_pcie: regulator-vddpcie {
reg_pcie: regulator-vddpcie@20c8140 {
reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddpcie";
regulator-min-microvolt = <725000>;
@ -664,7 +671,8 @@ reg_pcie: regulator-vddpcie {
anatop-max-voltage = <1450000>;
};
reg_soc: regulator-vddsoc {
reg_soc: regulator-vddsoc@20c8140 {
reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;

11
arch/arm/boot/dts/imx6ul.dtsi
View File

@ -542,8 +542,11 @@ anatop: anatop@20c8000 {
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg_3p0: regulator-3p0 {
reg_3p0: regulator-3p0@20c8110 {
reg = <0x20c8110>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2625000>;
@ -557,7 +560,8 @@ reg_3p0: regulator-3p0 {
anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
reg_arm: regulator-vddcore@20c8140 {
reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "cpu";
regulator-min-microvolt = <725000>;
@ -574,7 +578,8 @@ reg_arm: regulator-vddcore {
anatop-max-voltage = <1450000>;
};
reg_soc: regulator-vddsoc {
reg_soc: regulator-vddsoc@20c8140 {
reg = <0x20c8140>;
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;