mirror of https://gitee.com/openkylin/linux.git
staging: comedi: s626: remove 'allocatedBuf' from private data
This variable is only used to count the number of dma buffers allocated during the attach. If an allocation fails, the attach function exits with -ENOMEM. When this variable is checked later it will always be == 2. Just remove the variable and the check. This allows bringing the code back an indent level in s626_initialize(). Note, coding style issues in this function are not addressed yet. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Cc: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
f996ab29e9
commit
68ad0ae0ea
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@ -80,7 +80,6 @@ INSN_CONFIG instructions:
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struct s626_private {
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void __iomem *base_addr;
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short allocatedBuf;
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uint8_t ai_cmd_running; /* ai_cmd is running */
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uint8_t ai_continous; /* continous acquisition */
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int ai_sample_count; /* number of samples to acquire */
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@ -2443,24 +2442,18 @@ static int s626_allocate_dma_buffers(struct comedi_device *dev)
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void *addr;
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dma_addr_t appdma;
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devpriv->allocatedBuf = 0;
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addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);
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if (!addr)
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return -ENOMEM;
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devpriv->ANABuf.LogicalBase = addr;
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devpriv->ANABuf.PhysicalBase = appdma;
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devpriv->allocatedBuf++;
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addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);
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if (!addr)
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return -ENOMEM;
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devpriv->RPSBuf.LogicalBase = addr;
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devpriv->RPSBuf.PhysicalBase = appdma;
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devpriv->allocatedBuf++;
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return 0;
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}
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@ -2471,117 +2464,116 @@ static void s626_initialize(struct comedi_device *dev)
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/* uint16_t StartVal; */
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/* uint16_t index; */
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/* unsigned int data[16]; */
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dma_addr_t pPhysBuf;
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uint16_t chan;
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int i;
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if (devpriv->allocatedBuf == 2) {
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dma_addr_t pPhysBuf;
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uint16_t chan;
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/* enab DEBI and audio pins, enable I2C interface. */
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MC_ENABLE(P_MC1, MC1_DEBI | MC1_AUDIO | MC1_I2C);
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/* Configure DEBI operating mode. */
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WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 /* Local bus is 16 */
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/* bits wide. */
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| (DEBI_TOUT << DEBI_CFG_TOUT_BIT)
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/* enab DEBI and audio pins, enable I2C interface. */
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MC_ENABLE(P_MC1, MC1_DEBI | MC1_AUDIO | MC1_I2C);
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/* Configure DEBI operating mode. */
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WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 /* Local bus is 16 */
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/* bits wide. */
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| (DEBI_TOUT << DEBI_CFG_TOUT_BIT)
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/* Declare DEBI */
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/* transfer timeout */
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/* interval. */
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|DEBI_SWAP /* Set up byte lane */
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/* steering. */
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| DEBI_CFG_INTEL); /* Intel-compatible */
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/* local bus (DEBI */
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/* never times out). */
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/* Declare DEBI */
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/* transfer timeout */
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/* interval. */
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|DEBI_SWAP /* Set up byte lane */
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/* steering. */
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| DEBI_CFG_INTEL); /* Intel-compatible */
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/* local bus (DEBI */
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/* never times out). */
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/* DEBI INIT S626 WR7146( P_DEBICFG, DEBI_CFG_INTEL | DEBI_CFG_TOQ */
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/* | DEBI_CFG_INCQ| DEBI_CFG_16Q); //end */
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/* DEBI INIT S626 WR7146( P_DEBICFG, DEBI_CFG_INTEL | DEBI_CFG_TOQ */
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/* | DEBI_CFG_INCQ| DEBI_CFG_16Q); //end */
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/* Paging is disabled. */
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WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE); /* Disable MMU paging. */
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/* Paging is disabled. */
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WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE); /* Disable MMU paging. */
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/* Init GPIO so that ADC Start* is negated. */
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WR7146(P_GPIO, GPIO_BASE | GPIO1_HI);
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/* Init GPIO so that ADC Start* is negated. */
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WR7146(P_GPIO, GPIO_BASE | GPIO1_HI);
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/* IsBoardRevA is a boolean that indicates whether the board is RevA.
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*
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* VERSION 2.01 CHANGE: REV A & B BOARDS NOW SUPPORTED BY DYNAMIC
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* EEPROM ADDRESS SELECTION. Initialize the I2C interface, which
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* is used to access the onboard serial EEPROM. The EEPROM's I2C
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* DeviceAddress is hardwired to a value that is dependent on the
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* 626 board revision. On all board revisions, the EEPROM stores
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* TrimDAC calibration constants for analog I/O. On RevB and
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* higher boards, the DeviceAddress is hardwired to 0 to enable
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* the EEPROM to also store the PCI SubVendorID and SubDeviceID;
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* this is the address at which the SAA7146 expects a
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* configuration EEPROM to reside. On RevA boards, the EEPROM
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* device address, which is hardwired to 4, prevents the SAA7146
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* from retrieving PCI sub-IDs, so the SAA7146 uses its built-in
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* default values, instead.
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*/
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/* IsBoardRevA is a boolean that indicates whether the board is RevA.
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*
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* VERSION 2.01 CHANGE: REV A & B BOARDS NOW SUPPORTED BY DYNAMIC
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* EEPROM ADDRESS SELECTION. Initialize the I2C interface, which
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* is used to access the onboard serial EEPROM. The EEPROM's I2C
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* DeviceAddress is hardwired to a value that is dependent on the
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* 626 board revision. On all board revisions, the EEPROM stores
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* TrimDAC calibration constants for analog I/O. On RevB and
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* higher boards, the DeviceAddress is hardwired to 0 to enable
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* the EEPROM to also store the PCI SubVendorID and SubDeviceID;
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* this is the address at which the SAA7146 expects a
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* configuration EEPROM to reside. On RevA boards, the EEPROM
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* device address, which is hardwired to 4, prevents the SAA7146
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* from retrieving PCI sub-IDs, so the SAA7146 uses its built-in
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* default values, instead.
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*/
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/* devpriv->I2Cards= IsBoardRevA ? 0xA8 : 0xA0; // Set I2C EEPROM */
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/* DeviceType (0xA0) */
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/* and DeviceAddress<<1. */
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/* devpriv->I2Cards= IsBoardRevA ? 0xA8 : 0xA0; // Set I2C EEPROM */
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/* DeviceType (0xA0) */
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/* and DeviceAddress<<1. */
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devpriv->I2CAdrs = 0xA0; /* I2C device address for onboard */
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/* eeprom(revb) */
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devpriv->I2CAdrs = 0xA0; /* I2C device address for onboard */
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/* eeprom(revb) */
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/* Issue an I2C ABORT command to halt any I2C operation in */
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/* progress and reset BUSY flag. */
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WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT);
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/* Write I2C control: abort any I2C activity. */
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MC_ENABLE(P_MC2, MC2_UPLD_IIC);
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/* Invoke command upload */
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while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
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/* Issue an I2C ABORT command to halt any I2C operation in */
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/* progress and reset BUSY flag. */
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WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT);
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/* Write I2C control: abort any I2C activity. */
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MC_ENABLE(P_MC2, MC2_UPLD_IIC);
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/* Invoke command upload */
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while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
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;
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/* and wait for upload to complete. */
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/* Per SAA7146 data sheet, write to STATUS reg twice to
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* reset all I2C error flags. */
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for (i = 0; i < 2; i++) {
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WR7146(P_I2CSTAT, I2C_CLKSEL);
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/* Write I2C control: reset error flags. */
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MC_ENABLE(P_MC2, MC2_UPLD_IIC); /* Invoke command upload */
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while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
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;
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/* and wait for upload to complete. */
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/* and wait for upload to complete. */
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}
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/* Per SAA7146 data sheet, write to STATUS reg twice to
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* reset all I2C error flags. */
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for (i = 0; i < 2; i++) {
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WR7146(P_I2CSTAT, I2C_CLKSEL);
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/* Write I2C control: reset error flags. */
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MC_ENABLE(P_MC2, MC2_UPLD_IIC); /* Invoke command upload */
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while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
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;
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/* and wait for upload to complete. */
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}
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/* Init audio interface functional attributes: set DAC/ADC
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* serial clock rates, invert DAC serial clock so that
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* DAC data setup times are satisfied, enable DAC serial
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* clock out.
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*/
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/* Init audio interface functional attributes: set DAC/ADC
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* serial clock rates, invert DAC serial clock so that
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* DAC data setup times are satisfied, enable DAC serial
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* clock out.
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*/
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WR7146(P_ACON2, ACON2_INIT);
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WR7146(P_ACON2, ACON2_INIT);
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/* Set up TSL1 slot list, which is used to control the
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* accumulation of ADC data: RSD1 = shift data in on SD1.
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* SIB_A1 = store data uint8_t at next available location in
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* FB BUFFER1 register. */
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WR7146(P_TSL1, RSD1 | SIB_A1);
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/* Fetch ADC high data uint8_t. */
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WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS);
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/* Fetch ADC low data uint8_t; end of TSL1. */
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/* Set up TSL1 slot list, which is used to control the
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* accumulation of ADC data: RSD1 = shift data in on SD1.
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* SIB_A1 = store data uint8_t at next available location in
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* FB BUFFER1 register. */
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WR7146(P_TSL1, RSD1 | SIB_A1);
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/* Fetch ADC high data uint8_t. */
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WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS);
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/* Fetch ADC low data uint8_t; end of TSL1. */
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/* enab TSL1 slot list so that it executes all the time. */
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WR7146(P_ACON1, ACON1_ADCSTART);
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/* enab TSL1 slot list so that it executes all the time. */
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WR7146(P_ACON1, ACON1_ADCSTART);
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/* Initialize RPS registers used for ADC. */
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/* Initialize RPS registers used for ADC. */
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/* Physical start of RPS program. */
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WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
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/* Physical start of RPS program. */
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WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
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WR7146(P_RPSPAGE1, 0);
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/* RPS program performs no explicit mem writes. */
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WR7146(P_RPS1_TOUT, 0); /* Disable RPS timeouts. */
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WR7146(P_RPSPAGE1, 0);
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/* RPS program performs no explicit mem writes. */
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WR7146(P_RPS1_TOUT, 0); /* Disable RPS timeouts. */
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/* SAA7146 BUG WORKAROUND. Initialize SAA7146 ADC interface
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* to a known state by invoking ADCs until FB BUFFER 1
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* register shows that it is correctly receiving ADC data.
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* This is necessary because the SAA7146 ADC interface does
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* not start up in a defined state after a PCI reset.
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*/
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/* SAA7146 BUG WORKAROUND. Initialize SAA7146 ADC interface
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* to a known state by invoking ADCs until FB BUFFER 1
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* register shows that it is correctly receiving ADC data.
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* This is necessary because the SAA7146 ADC interface does
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* not start up in a defined state after a PCI reset.
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*/
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/* PollList = EOPL; // Create a simple polling */
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/* // list for analog input */
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@ -2609,124 +2601,121 @@ static void s626_initialize(struct comedi_device *dev)
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/* break; */
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/* } */
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/* end initADC */
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/* end initADC */
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/* init the DAC interface */
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/* init the DAC interface */
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/* Init Audio2's output DMAC attributes: burst length = 1
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* DWORD, threshold = 1 DWORD.
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*/
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WR7146(P_PCI_BT_A, 0);
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/* Init Audio2's output DMAC attributes: burst length = 1
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* DWORD, threshold = 1 DWORD.
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*/
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WR7146(P_PCI_BT_A, 0);
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/* Init Audio2's output DMA physical addresses. The protection
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* address is set to 1 DWORD past the base address so that a
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* single DWORD will be transferred each time a DMA transfer is
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* enabled. */
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/* Init Audio2's output DMA physical addresses. The protection
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* address is set to 1 DWORD past the base address so that a
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* single DWORD will be transferred each time a DMA transfer is
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* enabled. */
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pPhysBuf =
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devpriv->ANABuf.PhysicalBase +
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(DAC_WDMABUF_OS * sizeof(uint32_t));
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pPhysBuf = devpriv->ANABuf.PhysicalBase +
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(DAC_WDMABUF_OS * sizeof(uint32_t));
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WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf); /* Buffer base adrs. */
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WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); /* Protection address. */
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WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf); /* Buffer base adrs. */
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WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); /* Protection address. */
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/* Cache Audio2's output DMA buffer logical address. This is
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* where DAC data is buffered for A2 output DMA transfers. */
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devpriv->pDacWBuf =
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(uint32_t *) devpriv->ANABuf.LogicalBase + DAC_WDMABUF_OS;
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/* Cache Audio2's output DMA buffer logical address. This is
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* where DAC data is buffered for A2 output DMA transfers. */
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devpriv->pDacWBuf = (uint32_t *)devpriv->ANABuf.LogicalBase +
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DAC_WDMABUF_OS;
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/* Audio2's output channels does not use paging. The protection
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* violation handling bit is set so that the DMAC will
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* automatically halt and its PCI address pointer will be reset
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* when the protection address is reached. */
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/* Audio2's output channels does not use paging. The protection
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* violation handling bit is set so that the DMAC will
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* automatically halt and its PCI address pointer will be reset
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* when the protection address is reached. */
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WR7146(P_PAGEA2_OUT, 8);
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WR7146(P_PAGEA2_OUT, 8);
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/* Initialize time slot list 2 (TSL2), which is used to control
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* the clock generation for and serialization of data to be sent
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* to the DAC devices. Slot 0 is a NOP that is used to trap TSL
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* execution; this permits other slots to be safely modified
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* without first turning off the TSL sequencer (which is
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* apparently impossible to do). Also, SD3 (which is driven by a
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* pull-up resistor) is shifted in and stored to the MSB of
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* FB_BUFFER2 to be used as evidence that the slot sequence has
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* not yet finished executing.
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*/
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/* Initialize time slot list 2 (TSL2), which is used to control
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* the clock generation for and serialization of data to be sent
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* to the DAC devices. Slot 0 is a NOP that is used to trap TSL
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* execution; this permits other slots to be safely modified
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* without first turning off the TSL sequencer (which is
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* apparently impossible to do). Also, SD3 (which is driven by a
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* pull-up resistor) is shifted in and stored to the MSB of
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* FB_BUFFER2 to be used as evidence that the slot sequence has
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* not yet finished executing.
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*/
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SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS);
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/* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2. */
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SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS);
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/* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2. */
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/* Initialize slot 1, which is constant. Slot 1 causes a
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* DWORD to be transferred from audio channel 2's output FIFO
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* to the FIFO's output buffer so that it can be serialized
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* and sent to the DAC during subsequent slots. All remaining
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* slots are dynamically populated as required by the target
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* DAC device.
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*/
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SETVECT(1, LF_A2);
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/* Slot 1: Fetch DWORD from Audio2's output FIFO. */
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/* Initialize slot 1, which is constant. Slot 1 causes a
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* DWORD to be transferred from audio channel 2's output FIFO
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* to the FIFO's output buffer so that it can be serialized
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* and sent to the DAC during subsequent slots. All remaining
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* slots are dynamically populated as required by the target
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* DAC device.
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*/
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SETVECT(1, LF_A2);
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/* Slot 1: Fetch DWORD from Audio2's output FIFO. */
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/* Start DAC's audio interface (TSL2) running. */
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WR7146(P_ACON1, ACON1_DACSTART);
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/* Start DAC's audio interface (TSL2) running. */
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WR7146(P_ACON1, ACON1_DACSTART);
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/* end init DAC interface */
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/* end init DAC interface */
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/* Init Trim DACs to calibrated values. Do it twice because the
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* SAA7146 audio channel does not always reset properly and
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* sometimes causes the first few TrimDAC writes to malfunction.
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*/
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/* Init Trim DACs to calibrated values. Do it twice because the
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* SAA7146 audio channel does not always reset properly and
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* sometimes causes the first few TrimDAC writes to malfunction.
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*/
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LoadTrimDACs(dev);
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LoadTrimDACs(dev); /* Insurance. */
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LoadTrimDACs(dev);
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LoadTrimDACs(dev); /* Insurance. */
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/* Manually init all gate array hardware in case this is a soft
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* reset (we have no way of determining whether this is a warm
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* or cold start). This is necessary because the gate array will
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* reset only in response to a PCI hard reset; there is no soft
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* reset function. */
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/* Manually init all gate array hardware in case this is a soft
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* reset (we have no way of determining whether this is a warm
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* or cold start). This is necessary because the gate array will
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* reset only in response to a PCI hard reset; there is no soft
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* reset function. */
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/* Init all DAC outputs to 0V and init all DAC setpoint and
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* polarity images.
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*/
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for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
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SetDAC(dev, chan, 0);
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/* Init all DAC outputs to 0V and init all DAC setpoint and
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* polarity images.
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*/
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for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
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SetDAC(dev, chan, 0);
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/* Init image of WRMISC2 Battery Charger Enabled control bit.
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* This image is used when the state of the charger control bit,
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* which has no direct hardware readback mechanism, is queried.
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*/
|
||||
devpriv->ChargeEnabled = 0;
|
||||
/* Init image of WRMISC2 Battery Charger Enabled control bit.
|
||||
* This image is used when the state of the charger control bit,
|
||||
* which has no direct hardware readback mechanism, is queried.
|
||||
*/
|
||||
devpriv->ChargeEnabled = 0;
|
||||
|
||||
/* Init image of watchdog timer interval in WRMISC2. This image
|
||||
* maintains the value of the control bits of MISC2 are
|
||||
* continuously reset to zero as long as the WD timer is disabled.
|
||||
*/
|
||||
devpriv->WDInterval = 0;
|
||||
/* Init image of watchdog timer interval in WRMISC2. This image
|
||||
* maintains the value of the control bits of MISC2 are
|
||||
* continuously reset to zero as long as the WD timer is disabled.
|
||||
*/
|
||||
devpriv->WDInterval = 0;
|
||||
|
||||
/* Init Counter Interrupt enab mask for RDMISC2. This mask is
|
||||
* applied against MISC2 when testing to determine which timer
|
||||
* events are requesting interrupt service.
|
||||
*/
|
||||
devpriv->CounterIntEnabs = 0;
|
||||
/* Init Counter Interrupt enab mask for RDMISC2. This mask is
|
||||
* applied against MISC2 when testing to determine which timer
|
||||
* events are requesting interrupt service.
|
||||
*/
|
||||
devpriv->CounterIntEnabs = 0;
|
||||
|
||||
/* Init counters. */
|
||||
CountersInit(dev);
|
||||
/* Init counters. */
|
||||
CountersInit(dev);
|
||||
|
||||
/* Without modifying the state of the Battery Backup enab, disable
|
||||
* the watchdog timer, set DIO channels 0-5 to operate in the
|
||||
* standard DIO (vs. counter overflow) mode, disable the battery
|
||||
* charger, and reset the watchdog interval selector to zero.
|
||||
*/
|
||||
WriteMISC2(dev, (uint16_t) (DEBIread(dev,
|
||||
LP_RDMISC2) &
|
||||
MISC2_BATT_ENABLE));
|
||||
/* Without modifying the state of the Battery Backup enab, disable
|
||||
* the watchdog timer, set DIO channels 0-5 to operate in the
|
||||
* standard DIO (vs. counter overflow) mode, disable the battery
|
||||
* charger, and reset the watchdog interval selector to zero.
|
||||
*/
|
||||
WriteMISC2(dev, (uint16_t)(DEBIread(dev, LP_RDMISC2) &
|
||||
MISC2_BATT_ENABLE));
|
||||
|
||||
/* Initialize the digital I/O subsystem. */
|
||||
s626_dio_init(dev);
|
||||
/* Initialize the digital I/O subsystem. */
|
||||
s626_dio_init(dev);
|
||||
|
||||
/* enable interrupt test */
|
||||
/* writel(IRQ_GPIO3 | IRQ_RPS1,devpriv->base_addr+P_IER); */
|
||||
}
|
||||
/* enable interrupt test */
|
||||
/* writel(IRQ_GPIO3 | IRQ_RPS1,devpriv->base_addr+P_IER); */
|
||||
}
|
||||
|
||||
static int s626_attach_pci(struct comedi_device *dev, struct pci_dev *pcidev)
|
||||
|
|
|
|||
Loading…
Reference in New Issue