mirror of https://gitee.com/openkylin/linux.git
arm64: Kconfig: Re-jig CONFIG options for 52-bit VA
Enabling 52-bit VAs for userspace is pretty confusing, since it requires you to select "48-bit" virtual addressing in the Kconfig. Rework the logic so that 52-bit user virtual addressing is advertised in the "Virtual address space size" choice, along with some help text to describe its interaction with Pointer Authentication. The EXPERT-only option to force all user mappings to the 52-bit range is then made available immediately below the VA size selection. Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -682,15 +682,43 @@ config ARM64_VA_BITS_47
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config ARM64_VA_BITS_48
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bool "48-bit"
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config ARM64_USER_VA_BITS_52
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bool "52-bit (user)"
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depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
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help
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Enable 52-bit virtual addressing for userspace when explicitly
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requested via a hint to mmap(). The kernel will continue to
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use 48-bit virtual addresses for its own mappings.
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NOTE: Enabling 52-bit virtual addressing in conjunction with
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ARMv8.3 Pointer Authentication will result in the PAC being
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reduced from 7 bits to 3 bits, which may have a significant
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impact on its susceptibility to brute-force attacks.
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If unsure, select 48-bit virtual addressing instead.
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endchoice
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config ARM64_FORCE_52BIT
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bool "Force 52-bit virtual addresses for userspace"
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depends on ARM64_USER_VA_BITS_52 && EXPERT
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help
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For systems with 52-bit userspace VAs enabled, the kernel will attempt
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to maintain compatibility with older software by providing 48-bit VAs
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unless a hint is supplied to mmap.
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This configuration option disables the 48-bit compatibility logic, and
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forces all userspace addresses to be 52-bit on HW that supports it. One
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should only enable this configuration option for stress testing userspace
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memory management code. If unsure say N here.
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config ARM64_VA_BITS
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int
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default 36 if ARM64_VA_BITS_36
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default 39 if ARM64_VA_BITS_39
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default 42 if ARM64_VA_BITS_42
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default 47 if ARM64_VA_BITS_47
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default 48 if ARM64_VA_BITS_48
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default 48 if ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52
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choice
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prompt "Physical address space size"
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@ -716,10 +744,6 @@ config ARM64_PA_BITS_52
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endchoice
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config ARM64_52BIT_VA
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def_bool y
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depends on ARM64_VA_BITS_48 && ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
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config ARM64_PA_BITS
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int
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default 48 if ARM64_PA_BITS_48
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@ -1186,19 +1210,6 @@ config ARM64_CNP
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at runtime, and does not affect PEs that do not implement
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this feature.
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config ARM64_FORCE_52BIT
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bool "Force 52-bit virtual addresses for userspace"
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depends on ARM64_52BIT_VA && EXPERT
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help
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For systems with 52-bit userspace VAs enabled, the kernel will attempt
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to maintain compatibility with older software by providing 48-bit VAs
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unless a hint is supplied to mmap.
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This configuration option disables the 48-bit compatibility logic, and
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forces all userspace addresses to be 52-bit on HW that supports it. One
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should only enable this configuration option for stress testing userspace
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memory management code. If unsure say N here.
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endmenu
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config ARM64_SVE
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@ -549,7 +549,7 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU
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* ttbr: Value of ttbr to set, modified.
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*/
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.macro offset_ttbr1, ttbr
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#ifdef CONFIG_ARM64_52BIT_VA
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#ifdef CONFIG_ARM64_USER_VA_BITS_52
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orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
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#endif
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.endm
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@ -560,7 +560,7 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU
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* to be nop'ed out when dealing with 52-bit kernel VAs.
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*/
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.macro restore_ttbr1, ttbr
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#ifdef CONFIG_ARM64_52BIT_VA
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#ifdef CONFIG_ARM64_USER_VA_BITS_52
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bic \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
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#endif
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.endm
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@ -74,7 +74,7 @@ extern u64 idmap_ptrs_per_pgd;
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static inline bool __cpu_uses_extended_idmap(void)
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{
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if (IS_ENABLED(CONFIG_ARM64_52BIT_VA))
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if (IS_ENABLED(CONFIG_ARM64_USER_VA_BITS_52))
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return false;
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return unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS));
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@ -80,7 +80,7 @@
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#define PGDIR_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
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#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#ifdef CONFIG_ARM64_52BIT_VA
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#ifdef CONFIG_ARM64_USER_VA_BITS_52
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#define PTRS_PER_PGD (1 << (52 - PGDIR_SHIFT))
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#else
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#define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT))
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@ -310,7 +310,7 @@
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#define TTBR_BADDR_MASK_52 (((UL(1) << 46) - 1) << 2)
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#endif
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#ifdef CONFIG_ARM64_52BIT_VA
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#ifdef CONFIG_ARM64_USER_VA_BITS_52
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/* Must be at least 64-byte aligned to prevent corruption of the TTBR */
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#define TTBR1_BADDR_4852_OFFSET (((UL(1) << (52 - PGDIR_SHIFT)) - \
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(UL(1) << (48 - PGDIR_SHIFT))) * 8)
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@ -20,11 +20,11 @@
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#define __ASM_PROCESSOR_H
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#define KERNEL_DS UL(-1)
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#ifdef CONFIG_ARM64_52BIT_VA
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#ifdef CONFIG_ARM64_USER_VA_BITS_52
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#define USER_DS ((UL(1) << 52) - 1)
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#else
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#define USER_DS ((UL(1) << VA_BITS) - 1)
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#endif /* CONFIG_ARM64_52BIT_VA */
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#endif /* CONFIG_ARM64_USER_VA_BITS_52 */
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/*
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* On arm64 systems, unaligned accesses by the CPU are cheap, and so there is
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@ -318,7 +318,7 @@ __create_page_tables:
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adrp x0, idmap_pg_dir
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adrp x3, __idmap_text_start // __pa(__idmap_text_start)
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#ifdef CONFIG_ARM64_52BIT_VA
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#ifdef CONFIG_ARM64_USER_VA_BITS_52
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mrs_s x6, SYS_ID_AA64MMFR2_EL1
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and x6, x6, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
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mov x5, #52
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@ -800,7 +800,7 @@ ENTRY(__enable_mmu)
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ENDPROC(__enable_mmu)
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ENTRY(__cpu_secondary_check52bitva)
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#ifdef CONFIG_ARM64_52BIT_VA
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#ifdef CONFIG_ARM64_USER_VA_BITS_52
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ldr_l x0, vabits_user
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cmp x0, #52
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b.ne 2f
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@ -139,7 +139,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
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if (!cpu_online(cpu)) {
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pr_crit("CPU%u: failed to come online\n", cpu);
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if (IS_ENABLED(CONFIG_ARM64_52BIT_VA) && va52mismatch)
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if (IS_ENABLED(CONFIG_ARM64_USER_VA_BITS_52) && va52mismatch)
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pr_crit("CPU%u: does not support 52-bit VAs\n", cpu);
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ret = -EIO;
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@ -451,8 +451,8 @@ ENTRY(__cpu_setup)
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TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
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TCR_TBI0 | TCR_A1
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#ifdef CONFIG_ARM64_52BIT_VA
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ldr_l x9, vabits_user
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#ifdef CONFIG_ARM64_USER_VA_BITS_52
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ldr_l x9, vabits_user
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sub x9, xzr, x9
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add x9, x9, #64
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#else
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