mirror of https://gitee.com/openkylin/linux.git
[ARM] 3635/1: S3C24XX: Add S3C2412 core cpu support
Patch from Ben Dooks Add support for the Samsung S3C2412 and S3C2413 range of SoCs. This patch contains the core identification, debug macros, and basic register updates to get these to build. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Ben Dooks
Russell King
parent
a3ff55026e
commit
68d9ab394f
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@ -127,6 +127,20 @@ config CPU_S3C2410
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Support for S3C2410 and S3C2410A family from the S3C24XX line
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of Samsung Mobile CPUs.
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# internal node to signify if we are only dealing with an S3C2412
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config CPU_S3C2412_ONLY
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bool
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depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \
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!CPU_S3C2440 && !CPU_S3C2442 && CPU_S3C2412
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default y if CPU_S3C2412
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config CPU_S3C2412
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bool
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depends on ARCH_S3C2410
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help
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Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
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config CPU_S3C244X
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bool
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depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
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@ -24,6 +24,10 @@ obj-$(CONFIG_S3C2410_DMA) += dma.o
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obj-$(CONFIG_PM) += pm.o sleep.o
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obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
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# S3C2412 support
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obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
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#
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# S3C244X support
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obj-$(CONFIG_CPU_S3C244X) += s3c244x.o
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@ -44,6 +44,7 @@
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#include "clock.h"
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#include "s3c2400.h"
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#include "s3c2410.h"
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#include "s3c2412.h"
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#include "s3c244x.h"
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#include "s3c2440.h"
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#include "s3c2442.h"
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@ -62,6 +63,7 @@ struct cpu_table {
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static const char name_s3c2400[] = "S3C2400";
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static const char name_s3c2410[] = "S3C2410";
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static const char name_s3c2412[] = "S3C2412";
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static const char name_s3c2440[] = "S3C2440";
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static const char name_s3c2442[] = "S3C2442";
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static const char name_s3c2410a[] = "S3C2410A";
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@ -113,6 +115,15 @@ static struct cpu_table cpu_ids[] __initdata = {
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.init = s3c2442_init,
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.name = name_s3c2442
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},
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{
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.idcode = 0x32412001,
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.idmask = 0xffffffff,
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.map_io = s3c2412_map_io,
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.init_clocks = s3c2412_init_clocks,
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.init_uarts = s3c2412_init_uarts,
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.init = s3c2412_init,
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.name = name_s3c2412,
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},
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{
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.idcode = 0x0, /* S3C2400 doesn't have an idcode */
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.idmask = 0xffffffff,
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@ -171,6 +182,24 @@ void s3c24xx_set_board(struct s3c24xx_board *b)
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static struct cpu_table *cpu;
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static unsigned long s3c24xx_read_idcode_v5(void)
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{
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#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
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return __raw_readl(S3C2412_GSTATUS1);
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#else
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return 1UL; /* don't look like an 2400 */
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#endif
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}
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static unsigned long s3c24xx_read_idcode_v4(void)
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{
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#ifndef CONFIG_CPU_S3C2400
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return __raw_readl(S3C2410_GSTATUS1);
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#else
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return 0UL;
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#endif
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}
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void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
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{
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unsigned long idcode = 0x0;
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@ -178,9 +207,11 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
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/* initialise the io descriptors we need for initialisation */
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iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
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#ifndef CONFIG_CPU_S3C2400
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idcode = __raw_readl(S3C2410_GSTATUS1);
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#endif
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if (cpu_architecture() >= CPU_ARCH_ARMv5) {
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idcode = s3c24xx_read_idcode_v5();
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} else {
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idcode = s3c24xx_read_idcode_v4();
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}
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cpu = s3c_lookup_cpu(idcode);
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@ -74,5 +74,6 @@ extern struct sys_timer s3c24xx_timer;
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/* system device classes */
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extern struct sysdev_class s3c2410_sysclass;
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extern struct sysdev_class s3c2412_sysclass;
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extern struct sysdev_class s3c2440_sysclass;
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extern struct sysdev_class s3c2442_sysclass;
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@ -0,0 +1,195 @@
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/* linux/arch/arm/mach-s3c2410/s3c2412.c
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*
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* http://armlinux.simtec.co.uk/.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Modifications:
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* 16-May-2003 BJD Created initial version
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* 16-Aug-2003 BJD Fixed header files and copyright, added URL
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* 05-Sep-2003 BJD Moved to kernel v2.6
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* 18-Jan-2004 BJD Added serial port configuration
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* 21-Aug-2004 BJD Added new struct s3c2410_board handler
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* 28-Sep-2004 BJD Updates for new serial port bits
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* 04-Nov-2004 BJD Updated UART configuration process
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* 10-Jan-2005 BJD Removed s3c2410_clock_tick_rate
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* 13-Aug-2005 DA Removed UART from initial I/O mappings
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/sysdev.h>
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#include <linux/platform_device.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/arch/regs-clock.h>
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#include <asm/arch/regs-serial.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-gpioj.h>
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#include <asm/arch/regs-dsc.h>
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#include "s3c2412.h"
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#include "cpu.h"
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#include "devs.h"
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#include "clock.h"
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#include "pm.h"
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#ifndef CONFIG_CPU_S3C2412_ONLY
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void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
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#endif
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/* Initial IO mappings */
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static struct map_desc s3c2412_iodesc[] __initdata = {
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IODESC_ENT(CLKPWR),
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IODESC_ENT(LCD),
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IODESC_ENT(TIMER),
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IODESC_ENT(ADC),
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IODESC_ENT(WATCHDOG),
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};
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/* uart registration process */
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void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
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{
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s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
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/* rename devices that are s3c2412/s3c2413 specific */
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s3c_device_sdi.name = "s3c2412-sdi";
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s3c_device_nand.name = "s3c2412-nand";
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}
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/* s3c2412_map_io
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*
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* register the standard cpu IO areas, and any passed in from the
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* machine specific initialisation.
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*/
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void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
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{
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/* move base of IO */
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s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
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/* register our io-tables */
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iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
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iotable_init(mach_desc, mach_size);
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}
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void __init s3c2412_init_clocks(int xtal)
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{
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unsigned long tmp;
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unsigned long fclk;
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unsigned long hclk;
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unsigned long pclk;
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/* now we've got our machine bits initialised, work out what
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* clocks we've got */
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fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
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tmp = __raw_readl(S3C2410_CLKDIVN);
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/* work out clock scalings */
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hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
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hclk /= ((tmp & S3C2421_CLKDIVN_ARMDIVN) ? 2 : 1);
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pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
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/* print brieft summary of clocks, etc */
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printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
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print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
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/* initialise the clocks here, to allow other things like the
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* console to use them
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*/
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s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
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s3c2412_baseclk_add();
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}
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/* need to register class before we actually register the device, and
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* we also need to ensure that it has been initialised before any of the
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* drivers even try to use it (even if not on an s3c2412 based system)
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* as a driver which may support both 2410 and 2440 may try and use it.
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*/
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#ifdef CONFIG_PM
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static struct sleep_save s3c2412_sleep[] = {
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SAVE_ITEM(S3C2412_DSC0),
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SAVE_ITEM(S3C2412_DSC1),
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SAVE_ITEM(S3C2413_GPJDAT),
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SAVE_ITEM(S3C2413_GPJCON),
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SAVE_ITEM(S3C2413_GPJUP),
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/* save the sleep configuration anyway, just in case these
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* get damaged during wakeup */
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SAVE_ITEM(S3C2412_GPBSLPCON),
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SAVE_ITEM(S3C2412_GPCSLPCON),
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SAVE_ITEM(S3C2412_GPDSLPCON),
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SAVE_ITEM(S3C2412_GPESLPCON),
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SAVE_ITEM(S3C2412_GPFSLPCON),
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SAVE_ITEM(S3C2412_GPGSLPCON),
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SAVE_ITEM(S3C2412_GPHSLPCON),
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SAVE_ITEM(S3C2413_GPJSLPCON),
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};
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static int s3c2412_suspend(struct sys_device *dev, pm_message_t state)
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{
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s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
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return 0;
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}
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static int s3c2412_resume(struct sys_device *dev)
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{
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s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
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return 0;
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}
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#else
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#define s3c2412_suspend NULL
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#define s3c2412_resume NULL
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#endif
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struct sysdev_class s3c2412_sysclass = {
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set_kset_name("s3c2412-core"),
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.suspend = s3c2412_suspend,
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.resume = s3c2412_resume
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};
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static int __init s3c2412_core_init(void)
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{
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return sysdev_class_register(&s3c2412_sysclass);
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}
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core_initcall(s3c2412_core_init);
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static struct sys_device s3c2412_sysdev = {
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.cls = &s3c2412_sysclass,
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};
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int __init s3c2412_init(void)
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{
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printk("S3C2412: Initialising architecture\n");
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return sysdev_register(&s3c2412_sysdev);
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}
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@ -0,0 +1,29 @@
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/* arch/arm/mach-s3c2410/s3c2412.h
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*
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Header file for s3c2412 cpu support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifdef CONFIG_CPU_S3C2412
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extern int s3c2412_init(void);
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extern void s3c2412_map_io(struct map_desc *mach_desc, int size);
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extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
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extern void s3c2412_init_clocks(int xtal);
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extern int s3c2412_baseclk_add(void);
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#else
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#define s3c2412_init_clocks NULL
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#define s3c2412_init_uarts NULL
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#define s3c2412_map_io NULL
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#define s3c2412_init NULL
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#endif
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@ -33,7 +33,7 @@
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.endm
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.macro senduart,rd,rx
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str \rd, [\rx, # S3C2410_UTXH ]
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strb \rd, [\rx, # S3C2410_UTXH ]
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.endm
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.macro busyuart, rd, rx
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@ -42,6 +42,12 @@
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beq 1001f @
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@ FIFO enabled...
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1003:
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@ check for arm920 vs arm926. currently assume all arm926
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@ devices have an 64 byte FIFO identical to the s3c2440
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mrc p15, 0, \rd, c0, c0
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and \rd, \rd, #0xff0
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teq \rd, #0x260
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beq 1004f
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mrc p15, 0, \rd, c1, c0
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tst \rd, #1
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addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
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@ -50,7 +56,7 @@
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ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
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and \rd, \rd, #0x00ff0000
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teq \rd, #0x00440000 @ is it 2440?
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1004:
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ldr \rd, [ \rx, # S3C2410_UFSTAT ]
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moveq \rd, \rd, lsr #SHIFT_2440TXF
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tst \rd, #S3C2410_UFSTAT_TXFULL
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@ -236,4 +236,20 @@
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#define S3C24XX_PA_SPI S3C2410_PA_SPI
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#endif
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/* deal with the registers that move under the 2412/2413 */
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#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
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#ifndef __ASSEMBLY__
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extern void __iomem *s3c24xx_va_gpio2;
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#endif
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#ifdef CONFIG_CPU_S3C2412_ONLY
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#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
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#else
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#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
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#endif
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#else
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#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
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#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
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#endif
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#endif /* __ASM_ARCH_MAP_H */
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@ -23,6 +23,9 @@
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#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
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#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8)
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#define S3C2412_DSC0 S3C2410_GPIOREG(0xdc)
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#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0)
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#define S3C2440_SELECT_DSC0 (0)
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#define S3C2440_SELECT_DSC1 (1<<31)
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@ -45,7 +45,7 @@
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#define S3C24XX_MISCCR S3C2400_MISCCR
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#else
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#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x)
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#define S3C24XX_MISCCR S3C2410_MISCCR
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#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
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#endif /* CONFIG_CPU_S3C2400 */
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@ -73,9 +73,15 @@
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#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* not available on A */
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#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
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/* configure GPIO ports A..G */
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/* register address for the GPIO registers.
|
||||
* S3C24XX_GPIOREG2 is for the second set of registers in the
|
||||
* GPIO which move between s3c2410 and s3c2412 type systems */
|
||||
|
||||
#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
|
||||
#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
|
||||
|
||||
|
||||
/* configure GPIO ports A..G */
|
||||
|
||||
/* port A - S3C2410: 22bits, zero in bit X makes pin X output
|
||||
* S3C2400: 18bits, zero in bit X makes pin X output
|
||||
|
|
@ -953,11 +959,18 @@
|
|||
#define S3C2410_GPH10_OUTP (0x01 << 20)
|
||||
#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
|
||||
|
||||
/* The S3C2412 and S3C2413 move the GPJ register set to after
|
||||
* GPH, which means all registers after 0x80 are now offset by 0x10
|
||||
* for the 2412/2413 from the 2410/2440/2442
|
||||
*/
|
||||
|
||||
/* miscellaneous control */
|
||||
#define S3C2400_MISCCR S3C2410_GPIOREG(0x54)
|
||||
#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
|
||||
#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
|
||||
|
||||
#define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84)
|
||||
|
||||
/* see clock.h for dclk definitions */
|
||||
|
||||
/* pullup control on databus */
|
||||
|
|
@ -985,6 +998,8 @@
|
|||
#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
|
||||
#define S3C2410_MISCCR_CLK0_MASK (7<<4)
|
||||
|
||||
#define S3C2412_MISCCR_CLK0_RTC (2<<4)
|
||||
|
||||
#define S3C2410_MISCCR_CLK1_MPLL (0<<8)
|
||||
#define S3C2410_MISCCR_CLK1_UPLL (1<<8)
|
||||
#define S3C2410_MISCCR_CLK1_FCLK (2<<8)
|
||||
|
|
@ -993,6 +1008,8 @@
|
|||
#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
|
||||
#define S3C2410_MISCCR_CLK1_MASK (7<<8)
|
||||
|
||||
#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)
|
||||
|
||||
#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
|
||||
#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
|
||||
|
||||
|
|
@ -1000,7 +1017,7 @@
|
|||
|
||||
#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
|
||||
#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
|
||||
#define S3C2410_MISCCR_nEN_SCLKE (1<<19)
|
||||
#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */
|
||||
#define S3C2410_MISCCR_SDSLEEP (7<<17)
|
||||
|
||||
/* external interrupt control... */
|
||||
|
|
@ -1017,6 +1034,10 @@
|
|||
#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
|
||||
#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
|
||||
|
||||
#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)
|
||||
#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
|
||||
#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
|
||||
|
||||
/* values for S3C2410_EXTINT0/1/2 */
|
||||
#define S3C2410_EXTINT_LOWLEV (0x00)
|
||||
#define S3C2410_EXTINT_HILEV (0x01)
|
||||
|
|
@ -1030,6 +1051,11 @@
|
|||
#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
|
||||
#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
|
||||
|
||||
#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)
|
||||
#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)
|
||||
#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)
|
||||
#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)
|
||||
|
||||
/* values for interrupt filtering */
|
||||
#define S3C2410_EINTFLT_PCLK (0x00)
|
||||
#define S3C2410_EINTFLT_EXTCLK (1<<7)
|
||||
|
|
@ -1039,6 +1065,7 @@
|
|||
|
||||
/* GSTATUS have miscellaneous information in them
|
||||
*
|
||||
* These move between s3c2410 and s3c2412 style systems.
|
||||
*/
|
||||
|
||||
#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
|
||||
|
|
@ -1047,6 +1074,18 @@
|
|||
#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
|
||||
#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
|
||||
|
||||
#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC)
|
||||
#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0)
|
||||
#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4)
|
||||
#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8)
|
||||
#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC)
|
||||
|
||||
#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)
|
||||
#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)
|
||||
#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)
|
||||
#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)
|
||||
#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)
|
||||
|
||||
#define S3C2410_GSTATUS0_nWAIT (1<<3)
|
||||
#define S3C2410_GSTATUS0_NCON (1<<2)
|
||||
#define S3C2410_GSTATUS0_RnB (1<<1)
|
||||
|
|
@ -1054,6 +1093,7 @@
|
|||
|
||||
#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
|
||||
#define S3C2410_GSTATUS1_2410 (0x32410000)
|
||||
#define S3C2410_GSTATUS1_2412 (0x32412001)
|
||||
#define S3C2410_GSTATUS1_2440 (0x32440000)
|
||||
#define S3C2410_GSTATUS1_2442 (0x32440aaa)
|
||||
|
||||
|
|
@ -1077,5 +1117,22 @@
|
|||
#define S3C2400_OPENCR_OPC_MOSIDIS (0<<5)
|
||||
#define S3C2400_OPENCR_OPC_MOSIEN (1<<5)
|
||||
|
||||
/* 2412/2413 sleep configuration registers */
|
||||
|
||||
#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
|
||||
#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)
|
||||
#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)
|
||||
#define S3C2412_GPESLPCON S3C2410_GPIOREG(0x4C)
|
||||
#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)
|
||||
#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)
|
||||
#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)
|
||||
|
||||
/* definitions for each pin bit */
|
||||
#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
|
||||
#define S3C2412_SLPCON_HI(x) ( 0x01 << ((x) * 2))
|
||||
#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
|
||||
#define S3C2412_SLPCON_PDWN(x) ( 0x03 << ((x) * 2))
|
||||
#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2))
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_GPIO_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,11 @@
|
|||
#define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4)
|
||||
#define S3C2440_GPJUP S3C2410_GPIOREG(0xd8)
|
||||
|
||||
#define S3C2413_GPJCON S3C2410_GPIOREG(0x80)
|
||||
#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84)
|
||||
#define S3C2413_GPJUP S3C2410_GPIOREG(0x88)
|
||||
#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C)
|
||||
|
||||
#define S3C2440_GPJ0 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
|
||||
#define S3C2440_GPJ0_INP (0x00 << 0)
|
||||
#define S3C2440_GPJ0_OUTP (0x01 << 0)
|
||||
|
|
|
|||
Loading…
Reference in New Issue