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ARM i.MX51 clock: Fix regression since enabling MIPI/HSP clocks 

The MIPI/HSP clocks were recently turned on in the i.MX51 clock tree.
It turned out that the system does not work properly when the MIPI/HSP
clocks are enabled, but the IPU clock is disabled. This happens when
IPU support is disabled. In this case the IPU clock gets disabled when
the clock framework turns off unused clock in a late_initcall. This
is broken since:

| commit 9a2d4825a9
| Author: Sascha Hauer <s.hauer@pengutronix.de>
| Date:   Tue Jun 5 13:53:32 2012 +0200
|
|     ARM i.MX5: switch IPU clk support to devicetree bindings
|
|     The i.MX5 clk support has platform based clock bindings for the
|     IPU. IPU support is devicetree only, so move them over to devicetree
|     based bindings. Also, enable MIPI clocks which do not have a device
|     associated with, but still need to be enabled to do graphics on
|     i.MX51.

This patch fixes this by setting some reserved bits in the CCM as recommended
in the reference manual.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Sascha Hauer 2012-12-11 10:08:50 +01:00
parent 3e24b05ba3
commit 69155fd66d
1 changed files with 16 additions and 0 deletions
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16
arch/arm/mach-imx/clk-imx51-imx53.c
View File

@ -319,6 +319,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
unsigned long rate_ckih1, unsigned long rate_ckih2)
{
int i;
u32 val;
struct device_node *np;
clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
@ -390,6 +391,21 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
imx_print_silicon_rev("i.MX51", mx51_revision());
clk_disable_unprepare(clk[iim_gate]);
/*
* Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
* longer supported. Set to one for better power saving.
*
* The effect of not setting these bits is that MIPI clocks can't be
* enabled without the IPU clock being enabled aswell.
*/
val = readl(MXC_CCM_CCDR);
val |= 1 << 18;
writel(val, MXC_CCM_CCDR);
val = readl(MXC_CCM_CLPCR);
val |= 1 << 23;
writel(val, MXC_CCM_CLPCR);
return 0;
}