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staging: comedi: cb_pcidas: add whitespace to all the #define's
Add whitespace to all the #define's in the driver in order to improve the readability. Fix all the comments that are, or already were, > 80 characters. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Cc: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
7368348ccb
commit
6993197b75
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@ -81,64 +81,65 @@ analog triggering on 1602 series
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/* PCI vendor number of ComputerBoards/MeasurementComputing */
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/* PCI vendor number of ComputerBoards/MeasurementComputing */
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#define PCI_VENDOR_ID_CB 0x1307
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#define PCI_VENDOR_ID_CB 0x1307
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#define TIMER_BASE 100 /* 10MHz master clock */
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#define AI_BUFFER_SIZE 1024 /* maximum fifo size of any supported board */
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#define TIMER_BASE 100 /* 10MHz master clock */
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#define AO_BUFFER_SIZE 1024 /* maximum fifo size of any supported board */
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#define AI_BUFFER_SIZE 1024 /* max ai fifo size */
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#define NUM_CHANNELS_8800 8
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#define AO_BUFFER_SIZE 1024 /* max ao fifo size */
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#define NUM_CHANNELS_7376 1
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#define NUM_CHANNELS_8800 8
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#define NUM_CHANNELS_8402 2
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#define NUM_CHANNELS_7376 1
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#define NUM_CHANNELS_DAC08 1
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#define NUM_CHANNELS_8402 2
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#define NUM_CHANNELS_DAC08 1
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/* Control/Status registers */
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/* Control/Status registers */
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#define INT_ADCFIFO 0 /* INTERRUPT / ADC FIFO register */
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#define INT_ADCFIFO 0 /* INTERRUPT / ADC FIFO register */
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#define INT_EOS 0x1 /* interrupt end of scan */
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#define INT_EOS 0x1 /* int end of scan */
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#define INT_FHF 0x2 /* interrupt fifo half full */
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#define INT_FHF 0x2 /* int fifo half full */
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#define INT_FNE 0x3 /* interrupt fifo not empty */
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#define INT_FNE 0x3 /* int fifo not empty */
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#define INT_MASK 0x3 /* mask of interrupt select bits */
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#define INT_MASK 0x3 /* mask of int select bits */
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#define INTE 0x4 /* interrupt enable */
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#define INTE 0x4 /* int enable */
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#define DAHFIE 0x8 /* dac half full interrupt enable */
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#define DAHFIE 0x8 /* dac half full int enable */
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#define EOAIE 0x10 /* end of acquisition interrupt enable */
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#define EOAIE 0x10 /* end of acq. int enable */
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#define DAHFI 0x20 /* dac half full read status / write interrupt clear */
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#define DAHFI 0x20 /* dac half full status / clear */
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#define EOAI 0x40 /* read end of acq. interrupt status / write clear */
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#define EOAI 0x40 /* end of acq. int status / clear */
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#define INT 0x80 /* read interrupt status / write clear */
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#define INT 0x80 /* int status / clear */
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#define EOBI 0x200 /* read end of burst interrupt status */
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#define EOBI 0x200 /* end of burst int status */
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#define ADHFI 0x400 /* read half-full interrupt status */
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#define ADHFI 0x400 /* half-full int status */
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#define ADNEI 0x800 /* read fifo not empty interrupt latch status */
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#define ADNEI 0x800 /* fifo not empty int status (latch) */
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#define ADNE 0x1000 /* read, fifo not empty (realtime, not latched) status */
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#define ADNE 0x1000 /* fifo not empty status (realtime) */
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#define DAEMIE 0x1000 /* write, dac empty interrupt enable */
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#define DAEMIE 0x1000 /* dac empty int enable */
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#define LADFUL 0x2000 /* read fifo overflow / write clear */
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#define LADFUL 0x2000 /* fifo overflow / clear */
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#define DAEMI 0x4000 /* dac fifo empty interrupt status / write clear */
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#define DAEMI 0x4000 /* dac fifo empty int status / clear */
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#define ADCMUX_CONT 2 /* ADC CHANNEL MUX AND CONTROL register */
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#define ADCMUX_CONT 2 /* ADC CHANNEL MUX AND CONTROL reg */
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#define BEGIN_SCAN(x) ((x) & 0xf)
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#define BEGIN_SCAN(x) ((x) & 0xf)
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#define END_SCAN(x) (((x) & 0xf) << 4)
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#define END_SCAN(x) (((x) & 0xf) << 4)
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#define GAIN_BITS(x) (((x) & 0x3) << 8)
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#define GAIN_BITS(x) (((x) & 0x3) << 8)
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#define UNIP 0x800 /* Analog front-end unipolar for range */
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#define UNIP 0x800 /* Analog front-end unipolar mode */
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#define SE 0x400 /* Inputs in single-ended mode */
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#define SE 0x400 /* Inputs in single-ended mode */
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#define PACER_MASK 0x3000 /* pacer source bits */
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#define PACER_MASK 0x3000 /* pacer source bits */
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#define PACER_INT 0x1000 /* internal pacer */
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#define PACER_INT 0x1000 /* int. pacer */
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#define PACER_EXT_FALL 0x2000 /* external falling edge */
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#define PACER_EXT_FALL 0x2000 /* ext. falling edge */
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#define PACER_EXT_RISE 0x3000 /* external rising edge */
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#define PACER_EXT_RISE 0x3000 /* ext. rising edge */
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#define EOC 0x4000 /* adc not busy */
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#define EOC 0x4000 /* adc not busy */
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#define TRIG_CONTSTAT 4 /* TRIGGER CONTROL/STATUS register */
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#define TRIG_CONTSTAT 4 /* TRIGGER CONTROL/STATUS register */
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#define SW_TRIGGER 0x1 /* software start trigger */
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#define SW_TRIGGER 0x1 /* software start trigger */
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#define EXT_TRIGGER 0x2 /* external start trigger */
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#define EXT_TRIGGER 0x2 /* ext. start trigger */
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#define ANALOG_TRIGGER 0x3 /* external analog trigger */
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#define ANALOG_TRIGGER 0x3 /* ext. analog trigger */
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#define TRIGGER_MASK 0x3 /* mask of bits that determine start trigger */
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#define TRIGGER_MASK 0x3 /* start trigger mask */
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#define TGPOL 0x04 /* invert the edge/level of the external trigger (1602 only) */
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#define TGPOL 0x04 /* invert trigger (1602 only) */
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#define TGSEL 0x08 /* if set edge triggered, otherwise level trigerred (1602 only) */
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#define TGSEL 0x08 /* edge/level trigerred (1602 only) */
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#define TGEN 0x10 /* enable external start trigger */
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#define TGEN 0x10 /* enable external start trigger */
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#define BURSTE 0x20 /* burst mode enable */
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#define BURSTE 0x20 /* burst mode enable */
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#define XTRCL 0x80 /* clear external trigger */
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#define XTRCL 0x80 /* clear external trigger */
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#define CALIBRATION_REG 6 /* CALIBRATION register */
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#define CALIBRATION_REG 6 /* CALIBRATION register */
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#define SELECT_8800_BIT 0x100 /* select 8800 caldac */
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#define SELECT_8800_BIT 0x100 /* select 8800 caldac */
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#define SELECT_TRIMPOT_BIT 0x200 /* select ad7376 trim pot */
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#define SELECT_TRIMPOT_BIT 0x200 /* select ad7376 trim pot */
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#define SELECT_DAC08_BIT 0x400 /* select dac08 caldac */
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#define SELECT_DAC08_BIT 0x400 /* select dac08 caldac */
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#define CAL_SRC_BITS(x) (((x) & 0x7) << 11)
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#define CAL_SRC_BITS(x) (((x) & 0x7) << 11)
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#define CAL_EN_BIT 0x4000 /* read calibration source instead of analog input channel 0 */
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#define CAL_EN_BIT 0x4000 /* calibration source enable */
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#define SERIAL_DATA_IN_BIT 0x8000 /* serial data stream going to 8800 and 7376 */
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#define SERIAL_DATA_IN_BIT 0x8000 /* serial data bit going to caldac */
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#define DAC_CSR 0x8 /* dac control and status register */
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#define DAC_CSR 0x8 /* dac control and status register */
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#define DACEN 0x02 /* dac enable */
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#define DACEN 0x02 /* dac enable */
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@ -155,12 +156,12 @@ static inline unsigned int DAC_RANGE_MASK(unsigned int channel)
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};
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};
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/* bits for 1602 series only */
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/* bits for 1602 series only */
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#define DAC_EMPTY 0x1 /* fifo empty, read, write clear */
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#define DAC_EMPTY 0x1 /* fifo empty, read, write clear */
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#define DAC_START 0x4 /* start/arm fifo operations */
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#define DAC_START 0x4 /* start/arm fifo operations */
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#define DAC_PACER_MASK 0x18 /* bits that set pacer source */
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#define DAC_PACER_MASK 0x18 /* bits that set pacer source */
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#define DAC_PACER_INT 0x8 /* int. pacing */
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#define DAC_PACER_INT 0x8 /* int. pacing */
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#define DAC_PACER_EXT_FALL 0x10 /* ext. pacing, falling edge */
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#define DAC_PACER_EXT_FALL 0x10 /* ext. pacing, falling edge */
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#define DAC_PACER_EXT_RISE 0x18 /* ext. pacing, rising edge */
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#define DAC_PACER_EXT_RISE 0x18 /* ext. pacing, rising edge */
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static inline unsigned int DAC_CHAN_EN(unsigned int channel)
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static inline unsigned int DAC_CHAN_EN(unsigned int channel)
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{
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{
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@ -168,13 +169,13 @@ static inline unsigned int DAC_CHAN_EN(unsigned int channel)
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};
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};
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/* analog input fifo */
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/* analog input fifo */
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#define ADCDATA 0 /* ADC DATA register */
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#define ADCDATA 0 /* ADC DATA register */
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#define ADCFIFOCLR 2 /* ADC FIFO CLEAR */
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#define ADCFIFOCLR 2 /* ADC FIFO CLEAR */
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/* pacer, counter, dio registers */
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/* pacer, counter, dio registers */
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#define ADC8254 0
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#define ADC8254 0
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#define DIO_8255 4
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#define DIO_8255 4
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#define DAC8254 8
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#define DAC8254 8
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/* analog output registers for 100x, 1200 series */
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/* analog output registers for 100x, 1200 series */
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static inline unsigned int DAC_DATA_REG(unsigned int channel)
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static inline unsigned int DAC_DATA_REG(unsigned int channel)
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@ -183,11 +184,11 @@ static inline unsigned int DAC_DATA_REG(unsigned int channel)
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}
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}
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/* analog output registers for 1602 series*/
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/* analog output registers for 1602 series*/
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#define DACDATA 0 /* DAC DATA register */
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#define DACDATA 0 /* DAC DATA register */
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#define DACFIFOCLR 2 /* DAC FIFO CLEAR */
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#define DACFIFOCLR 2 /* DAC FIFO CLEAR */
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#define IS_UNIPOLAR 0x4 /* unipolar range mask */
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/* bit in hexadecimal representation of range index that indicates unipolar input range */
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#define IS_UNIPOLAR 0x4
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/* analog input ranges for most boards */
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/* analog input ranges for most boards */
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static const struct comedi_lrange cb_pcidas_ranges = {
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static const struct comedi_lrange cb_pcidas_ranges = {
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8,
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8,
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