mirror of https://gitee.com/openkylin/linux.git
KVM/ARM updates for v4.11-rc2
vgic updates: - Honour disabling the ITS - Don't deadlock when deactivating own interrupts via MMIO - Correctly expose the lact of IRQ/FIQ bypass on GICv3 I/O virtualization: - Make KVM_CAP_NR_MEMSLOTS big enough for large guests with many PCIe devices General bug fixes: - Gracefully handle exception generated with syndroms that the host doesn't understand - Properly invalidate TLBs on VHE systems -----BEGIN PGP SIGNATURE----- iQFJBAABCAAzFiEEaVjJ8iM8Xp1syoGKqzCcdLk7HqEFAljBIgcVHG1hcmMuenlu Z2llckBhcm0uY29tAAoJEKswnHS5Ox6hXKUH/j2K+UJrvBISpjEnF8v1rXcXSMxZ 8z/MT/bsmjpX0t/+YBpmNYrEA06RCWGDt4J5kGnl4imS+Xtqr16XeKW/rrOlydE5 JlvKXs31AWxym9ASnmLf8A2rODNtOWXOUrbYLm6VDUHb8E5ou1U2ywSVOvXqMSYD pHtoD9PRqIQqxJtcV5DtJ3Xgg7AsIdmeBtBz1UGmi9rwKMk1hfwXrIPb2HCraiuY /11RdIuWy5py62fi+x+coyXtpbCyhDDcGjiHHu4eqCqXtIZ91KkDSPFXfx14PhHB UTTUBPKFwCdY+FFsWJtX20I+jGQt1nVL1yMbytdVJbmOixtHPQkjz17ReRU= =hplc -----END PGP SIGNATURE----- Merge tag 'kvm-arm-for-4.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm KVM/ARM updates for v4.11-rc2 vgic updates: - Honour disabling the ITS - Don't deadlock when deactivating own interrupts via MMIO - Correctly expose the lact of IRQ/FIQ bypass on GICv3 I/O virtualization: - Make KVM_CAP_NR_MEMSLOTS big enough for large guests with many PCIe devices General bug fixes: - Gracefully handle exception generated with syndroms that the host doesn't understand - Properly invalidate TLBs on VHE systems
This commit is contained in:
Radim Krčmář
commit
6a29b512cf
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@ -951,6 +951,10 @@ This ioctl allows the user to create or modify a guest physical memory
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slot. When changing an existing slot, it may be moved in the guest
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physical memory space, or its flags may be modified. It may not be
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resized. Slots may not overlap in guest physical address space.
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Bits 0-15 of "slot" specifies the slot id and this value should be
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less than the maximum number of user memory slots supported per VM.
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The maximum allowed slots can be queried using KVM_CAP_NR_MEMSLOTS,
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if this capability is supported by the architecture.
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If KVM_CAP_MULTI_ADDRESS_SPACE is available, bits 16-31 of "slot"
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specifies the address space which is being modified. They must be
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@ -209,6 +209,7 @@
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#define HSR_EC_IABT_HYP (0x21)
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#define HSR_EC_DABT (0x24)
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#define HSR_EC_DABT_HYP (0x25)
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#define HSR_EC_MAX (0x3f)
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#define HSR_WFI_IS_WFE (_AC(1, UL) << 0)
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@ -30,7 +30,6 @@
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#define __KVM_HAVE_ARCH_INTC_INITIALIZED
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#define KVM_USER_MEM_SLOTS 32
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#define KVM_PRIVATE_MEM_SLOTS 4
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#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
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#define KVM_HAVE_ONE_REG
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#define KVM_HALT_POLL_NS_DEFAULT 500000
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@ -221,6 +221,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
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case KVM_CAP_MAX_VCPUS:
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r = KVM_MAX_VCPUS;
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break;
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case KVM_CAP_NR_MEMSLOTS:
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r = KVM_USER_MEM_SLOTS;
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break;
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case KVM_CAP_MSI_DEVID:
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if (!kvm)
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r = -EINVAL;
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@ -79,7 +79,19 @@ static int kvm_handle_wfx(struct kvm_vcpu *vcpu, struct kvm_run *run)
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return 1;
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}
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static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu, struct kvm_run *run)
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{
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u32 hsr = kvm_vcpu_get_hsr(vcpu);
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kvm_pr_unimpl("Unknown exception class: hsr: %#08x\n",
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hsr);
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kvm_inject_undefined(vcpu);
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return 1;
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}
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static exit_handle_fn arm_exit_handlers[] = {
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[0 ... HSR_EC_MAX] = kvm_handle_unknown_ec,
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[HSR_EC_WFI] = kvm_handle_wfx,
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[HSR_EC_CP15_32] = kvm_handle_cp15_32,
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[HSR_EC_CP15_64] = kvm_handle_cp15_64,
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@ -98,13 +110,6 @@ static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu)
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{
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u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
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if (hsr_ec >= ARRAY_SIZE(arm_exit_handlers) ||
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!arm_exit_handlers[hsr_ec]) {
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kvm_err("Unknown exception class: hsr: %#08x\n",
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(unsigned int)kvm_vcpu_get_hsr(vcpu));
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BUG();
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}
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return arm_exit_handlers[hsr_ec];
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}
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@ -30,8 +30,7 @@
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#define __KVM_HAVE_ARCH_INTC_INITIALIZED
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#define KVM_USER_MEM_SLOTS 32
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#define KVM_PRIVATE_MEM_SLOTS 4
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#define KVM_USER_MEM_SLOTS 512
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#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
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#define KVM_HALT_POLL_NS_DEFAULT 500000
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@ -135,7 +135,19 @@ static int kvm_handle_guest_debug(struct kvm_vcpu *vcpu, struct kvm_run *run)
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return ret;
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}
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static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu, struct kvm_run *run)
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{
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u32 hsr = kvm_vcpu_get_hsr(vcpu);
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kvm_pr_unimpl("Unknown exception class: hsr: %#08x -- %s\n",
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hsr, esr_get_class_string(hsr));
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kvm_inject_undefined(vcpu);
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return 1;
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}
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static exit_handle_fn arm_exit_handlers[] = {
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[0 ... ESR_ELx_EC_MAX] = kvm_handle_unknown_ec,
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[ESR_ELx_EC_WFx] = kvm_handle_wfx,
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[ESR_ELx_EC_CP15_32] = kvm_handle_cp15_32,
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[ESR_ELx_EC_CP15_64] = kvm_handle_cp15_64,
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@ -162,13 +174,6 @@ static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu)
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u32 hsr = kvm_vcpu_get_hsr(vcpu);
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u8 hsr_ec = ESR_ELx_EC(hsr);
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if (hsr_ec >= ARRAY_SIZE(arm_exit_handlers) ||
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!arm_exit_handlers[hsr_ec]) {
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kvm_err("Unknown exception class: hsr: %#08x -- %s\n",
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hsr, esr_get_class_string(hsr));
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BUG();
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}
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return arm_exit_handlers[hsr_ec];
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}
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@ -18,14 +18,62 @@
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#include <asm/kvm_hyp.h>
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#include <asm/tlbflush.h>
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static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm)
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{
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u64 val;
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/*
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* With VHE enabled, we have HCR_EL2.{E2H,TGE} = {1,1}, and
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* most TLB operations target EL2/EL0. In order to affect the
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* guest TLBs (EL1/EL0), we need to change one of these two
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* bits. Changing E2H is impossible (goodbye TTBR1_EL2), so
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* let's flip TGE before executing the TLB operation.
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*/
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write_sysreg(kvm->arch.vttbr, vttbr_el2);
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val = read_sysreg(hcr_el2);
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val &= ~HCR_TGE;
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write_sysreg(val, hcr_el2);
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isb();
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}
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static void __hyp_text __tlb_switch_to_guest_nvhe(struct kvm *kvm)
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{
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write_sysreg(kvm->arch.vttbr, vttbr_el2);
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isb();
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}
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static hyp_alternate_select(__tlb_switch_to_guest,
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__tlb_switch_to_guest_nvhe,
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__tlb_switch_to_guest_vhe,
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ARM64_HAS_VIRT_HOST_EXTN);
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static void __hyp_text __tlb_switch_to_host_vhe(struct kvm *kvm)
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{
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/*
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* We're done with the TLB operation, let's restore the host's
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* view of HCR_EL2.
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*/
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write_sysreg(0, vttbr_el2);
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write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
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}
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static void __hyp_text __tlb_switch_to_host_nvhe(struct kvm *kvm)
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{
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write_sysreg(0, vttbr_el2);
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}
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static hyp_alternate_select(__tlb_switch_to_host,
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__tlb_switch_to_host_nvhe,
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__tlb_switch_to_host_vhe,
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ARM64_HAS_VIRT_HOST_EXTN);
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void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
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{
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dsb(ishst);
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/* Switch to requested VMID */
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kvm = kern_hyp_va(kvm);
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write_sysreg(kvm->arch.vttbr, vttbr_el2);
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isb();
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__tlb_switch_to_guest()(kvm);
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/*
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* We could do so much better if we had the VA as well.
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@ -46,7 +94,7 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
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dsb(ish);
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isb();
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write_sysreg(0, vttbr_el2);
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__tlb_switch_to_host()(kvm);
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}
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void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm)
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@ -55,14 +103,13 @@ void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm)
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/* Switch to requested VMID */
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kvm = kern_hyp_va(kvm);
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write_sysreg(kvm->arch.vttbr, vttbr_el2);
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isb();
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__tlb_switch_to_guest()(kvm);
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__tlbi(vmalls12e1is);
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dsb(ish);
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isb();
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write_sysreg(0, vttbr_el2);
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__tlb_switch_to_host()(kvm);
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}
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void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu)
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@ -70,14 +117,13 @@ void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu)
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struct kvm *kvm = kern_hyp_va(kern_hyp_va(vcpu)->kvm);
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/* Switch to requested VMID */
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write_sysreg(kvm->arch.vttbr, vttbr_el2);
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isb();
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__tlb_switch_to_guest()(kvm);
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__tlbi(vmalle1);
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dsb(nsh);
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isb();
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write_sysreg(0, vttbr_el2);
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__tlb_switch_to_host()(kvm);
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}
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void __hyp_text __kvm_flush_vm_context(void)
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@ -373,6 +373,8 @@
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#define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT)
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#define ICC_IGRPEN1_EL1_SHIFT 0
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#define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT)
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#define ICC_SRE_EL1_DIB (1U << 2)
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#define ICC_SRE_EL1_DFB (1U << 1)
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#define ICC_SRE_EL1_SRE (1U << 0)
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/*
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@ -360,29 +360,6 @@ static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu)
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return ret;
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}
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static unsigned long vgic_mmio_read_its_ctlr(struct kvm *vcpu,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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u32 reg = 0;
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mutex_lock(&its->cmd_lock);
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if (its->creadr == its->cwriter)
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reg |= GITS_CTLR_QUIESCENT;
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if (its->enabled)
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reg |= GITS_CTLR_ENABLE;
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mutex_unlock(&its->cmd_lock);
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return reg;
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}
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static void vgic_mmio_write_its_ctlr(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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its->enabled = !!(val & GITS_CTLR_ENABLE);
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}
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static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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@ -1161,33 +1138,16 @@ static void vgic_mmio_write_its_cbaser(struct kvm *kvm, struct vgic_its *its,
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#define ITS_CMD_SIZE 32
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#define ITS_CMD_OFFSET(reg) ((reg) & GENMASK(19, 5))
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/*
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* By writing to CWRITER the guest announces new commands to be processed.
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* To avoid any races in the first place, we take the its_cmd lock, which
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* protects our ring buffer variables, so that there is only one user
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* per ITS handling commands at a given time.
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*/
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static void vgic_mmio_write_its_cwriter(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len,
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unsigned long val)
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/* Must be called with the cmd_lock held. */
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static void vgic_its_process_commands(struct kvm *kvm, struct vgic_its *its)
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{
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gpa_t cbaser;
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u64 cmd_buf[4];
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u32 reg;
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if (!its)
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/* Commands are only processed when the ITS is enabled. */
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if (!its->enabled)
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return;
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mutex_lock(&its->cmd_lock);
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reg = update_64bit_reg(its->cwriter, addr & 7, len, val);
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reg = ITS_CMD_OFFSET(reg);
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if (reg >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
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mutex_unlock(&its->cmd_lock);
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return;
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}
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its->cwriter = reg;
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cbaser = CBASER_ADDRESS(its->cbaser);
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while (its->cwriter != its->creadr) {
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@ -1207,6 +1167,34 @@ static void vgic_mmio_write_its_cwriter(struct kvm *kvm, struct vgic_its *its,
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if (its->creadr == ITS_CMD_BUFFER_SIZE(its->cbaser))
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its->creadr = 0;
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}
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}
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/*
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* By writing to CWRITER the guest announces new commands to be processed.
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* To avoid any races in the first place, we take the its_cmd lock, which
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* protects our ring buffer variables, so that there is only one user
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* per ITS handling commands at a given time.
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*/
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static void vgic_mmio_write_its_cwriter(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u64 reg;
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if (!its)
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return;
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mutex_lock(&its->cmd_lock);
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reg = update_64bit_reg(its->cwriter, addr & 7, len, val);
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reg = ITS_CMD_OFFSET(reg);
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if (reg >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
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mutex_unlock(&its->cmd_lock);
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return;
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}
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its->cwriter = reg;
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vgic_its_process_commands(kvm, its);
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mutex_unlock(&its->cmd_lock);
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}
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|
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@ -1287,6 +1275,39 @@ static void vgic_mmio_write_its_baser(struct kvm *kvm,
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*regptr = reg;
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}
|
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static unsigned long vgic_mmio_read_its_ctlr(struct kvm *vcpu,
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struct vgic_its *its,
|
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gpa_t addr, unsigned int len)
|
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{
|
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u32 reg = 0;
|
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|
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mutex_lock(&its->cmd_lock);
|
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if (its->creadr == its->cwriter)
|
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reg |= GITS_CTLR_QUIESCENT;
|
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if (its->enabled)
|
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reg |= GITS_CTLR_ENABLE;
|
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mutex_unlock(&its->cmd_lock);
|
||||
|
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return reg;
|
||||
}
|
||||
|
||||
static void vgic_mmio_write_its_ctlr(struct kvm *kvm, struct vgic_its *its,
|
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gpa_t addr, unsigned int len,
|
||||
unsigned long val)
|
||||
{
|
||||
mutex_lock(&its->cmd_lock);
|
||||
|
||||
its->enabled = !!(val & GITS_CTLR_ENABLE);
|
||||
|
||||
/*
|
||||
* Try to process any pending commands. This function bails out early
|
||||
* if the ITS is disabled or no commands have been queued.
|
||||
*/
|
||||
vgic_its_process_commands(kvm, its);
|
||||
|
||||
mutex_unlock(&its->cmd_lock);
|
||||
}
|
||||
|
||||
#define REGISTER_ITS_DESC(off, rd, wr, length, acc) \
|
||||
{ \
|
||||
.reg_offset = off, \
|
||||
|
|
|
|||
|
|
@ -180,21 +180,37 @@ unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
|
|||
static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
|
||||
bool new_active_state)
|
||||
{
|
||||
struct kvm_vcpu *requester_vcpu;
|
||||
spin_lock(&irq->irq_lock);
|
||||
|
||||
/*
|
||||
* The vcpu parameter here can mean multiple things depending on how
|
||||
* this function is called; when handling a trap from the kernel it
|
||||
* depends on the GIC version, and these functions are also called as
|
||||
* part of save/restore from userspace.
|
||||
*
|
||||
* Therefore, we have to figure out the requester in a reliable way.
|
||||
*
|
||||
* When accessing VGIC state from user space, the requester_vcpu is
|
||||
* NULL, which is fine, because we guarantee that no VCPUs are running
|
||||
* when accessing VGIC state from user space so irq->vcpu->cpu is
|
||||
* always -1.
|
||||
*/
|
||||
requester_vcpu = kvm_arm_get_running_vcpu();
|
||||
|
||||
/*
|
||||
* If this virtual IRQ was written into a list register, we
|
||||
* have to make sure the CPU that runs the VCPU thread has
|
||||
* synced back LR state to the struct vgic_irq. We can only
|
||||
* know this for sure, when either this irq is not assigned to
|
||||
* anyone's AP list anymore, or the VCPU thread is not
|
||||
* running on any CPUs.
|
||||
* synced back the LR state to the struct vgic_irq.
|
||||
*
|
||||
* In the opposite case, we know the VCPU thread may be on its
|
||||
* way back from the guest and still has to sync back this
|
||||
* IRQ, so we release and re-acquire the spin_lock to let the
|
||||
* other thread sync back the IRQ.
|
||||
* As long as the conditions below are true, we know the VCPU thread
|
||||
* may be on its way back from the guest (we kicked the VCPU thread in
|
||||
* vgic_change_active_prepare) and still has to sync back this IRQ,
|
||||
* so we release and re-acquire the spin_lock to let the other thread
|
||||
* sync back the IRQ.
|
||||
*/
|
||||
while (irq->vcpu && /* IRQ may have state in an LR somewhere */
|
||||
irq->vcpu != requester_vcpu && /* Current thread is not the VCPU thread */
|
||||
irq->vcpu->cpu != -1) /* VCPU thread is running */
|
||||
cond_resched_lock(&irq->irq_lock);
|
||||
|
||||
|
|
|
|||
|
|
@ -229,10 +229,13 @@ void vgic_v3_enable(struct kvm_vcpu *vcpu)
|
|||
/*
|
||||
* If we are emulating a GICv3, we do it in an non-GICv2-compatible
|
||||
* way, so we force SRE to 1 to demonstrate this to the guest.
|
||||
* Also, we don't support any form of IRQ/FIQ bypass.
|
||||
* This goes with the spec allowing the value to be RAO/WI.
|
||||
*/
|
||||
if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
|
||||
vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
|
||||
vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
|
||||
ICC_SRE_EL1_DFB |
|
||||
ICC_SRE_EL1_SRE);
|
||||
vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
|
||||
} else {
|
||||
vgic_v3->vgic_sre = 0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue