mirror of https://gitee.com/openkylin/linux.git
i2c: uniphier_f: add UniPhier FIFO-builtin I2C driver
Add support for on-chip I2C controller used on newer UniPhier SoCs such as PH1-Pro4, PH1-Pro5, etc. This adapter is equipped with 8-depth TX/RX FIFOs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Masahiro Yamada
Wolfram Sang
parent
dd6fd4a327
commit
6a62974b66
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@ -0,0 +1,25 @@
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UniPhier I2C controller (FIFO-builtin)
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Required properties:
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- compatible: should be "socionext,uniphier-fi2c".
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- #address-cells: should be 1.
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- #size-cells: should be 0.
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- reg: offset and length of the register set for the device.
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- interrupts: a single interrupt specifier.
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- clocks: phandle to the input clock.
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Optional properties:
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- clock-frequency: desired I2C bus frequency in Hz. The maximum supported
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value is 400000. Defaults to 100000 if not specified.
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Examples:
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i2c0: i2c@58780000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58780000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 4>;
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clocks = <&i2c_clk>;
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clock-frequency = <100000>;
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};
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@ -910,6 +910,14 @@ config I2C_UNIPHIER
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the UniPhier FIFO-less I2C interface embedded in PH1-LD4, PH1-sLD8,
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or older UniPhier SoCs.
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config I2C_UNIPHIER_F
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tristate "UniPhier FIFO-builtin I2C controller"
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depends on ARCH_UNIPHIER
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help
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If you say yes to this option, support will be included for
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the UniPhier FIFO-builtin I2C interface embedded in PH1-Pro4,
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PH1-Pro5, or newer UniPhier SoCs.
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config I2C_VERSATILE
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tristate "ARM Versatile/Realview I2C bus support"
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depends on ARCH_VERSATILE || ARCH_REALVIEW || ARCH_VEXPRESS
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@ -88,6 +88,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
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obj-$(CONFIG_I2C_SUN6I_P2WI) += i2c-sun6i-p2wi.o
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obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o
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obj-$(CONFIG_I2C_UNIPHIER) += i2c-uniphier.o
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obj-$(CONFIG_I2C_UNIPHIER_F) += i2c-uniphier-f.o
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obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
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obj-$(CONFIG_I2C_WMT) += i2c-wmt.o
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obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
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@ -0,0 +1,584 @@
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#define UNIPHIER_FI2C_CR 0x00 /* control register */
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#define UNIPHIER_FI2C_CR_MST BIT(3) /* master mode */
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#define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */
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#define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */
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#define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */
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#define UNIPHIER_FI2C_DTTX 0x04 /* TX FIFO */
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#define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (slave addr) */
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#define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */
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#define UNIPHIER_FI2C_DTRX 0x04 /* RX FIFO */
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#define UNIPHIER_FI2C_SLAD 0x0c /* slave address */
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#define UNIPHIER_FI2C_CYC 0x10 /* clock cycle control */
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#define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */
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#define UNIPHIER_FI2C_SSUT 0x18 /* restart/stop setup time control */
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#define UNIPHIER_FI2C_DSUT 0x1c /* data setup time control */
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#define UNIPHIER_FI2C_INT 0x20 /* interrupt status */
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#define UNIPHIER_FI2C_IE 0x24 /* interrupt enable */
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#define UNIPHIER_FI2C_IC 0x28 /* interrupt clear */
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#define UNIPHIER_FI2C_INT_TE BIT(9) /* TX FIFO empty */
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#define UNIPHIER_FI2C_INT_RF BIT(8) /* RX FIFO full */
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#define UNIPHIER_FI2C_INT_TC BIT(7) /* send complete (STOP) */
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#define UNIPHIER_FI2C_INT_RC BIT(6) /* receive complete (STOP) */
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#define UNIPHIER_FI2C_INT_TB BIT(5) /* sent specified bytes */
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#define UNIPHIER_FI2C_INT_RB BIT(4) /* received specified bytes */
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#define UNIPHIER_FI2C_INT_NA BIT(2) /* no ACK */
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#define UNIPHIER_FI2C_INT_AL BIT(1) /* arbitration lost */
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#define UNIPHIER_FI2C_SR 0x2c /* status register */
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#define UNIPHIER_FI2C_SR_DB BIT(12) /* device busy */
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#define UNIPHIER_FI2C_SR_STS BIT(11) /* stop condition detected */
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#define UNIPHIER_FI2C_SR_BB BIT(8) /* bus busy */
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#define UNIPHIER_FI2C_SR_RFF BIT(3) /* RX FIFO full */
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#define UNIPHIER_FI2C_SR_RNE BIT(2) /* RX FIFO not empty */
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#define UNIPHIER_FI2C_SR_TNF BIT(1) /* TX FIFO not full */
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#define UNIPHIER_FI2C_SR_TFE BIT(0) /* TX FIFO empty */
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#define UNIPHIER_FI2C_RST 0x34 /* reset control */
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#define UNIPHIER_FI2C_RST_TBRST BIT(2) /* clear TX FIFO */
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#define UNIPHIER_FI2C_RST_RBRST BIT(1) /* clear RX FIFO */
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#define UNIPHIER_FI2C_RST_RST BIT(0) /* forcible bus reset */
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#define UNIPHIER_FI2C_BM 0x38 /* bus monitor */
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#define UNIPHIER_FI2C_BM_SDAO BIT(3) /* output for SDA line */
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#define UNIPHIER_FI2C_BM_SDAS BIT(2) /* readback of SDA line */
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#define UNIPHIER_FI2C_BM_SCLO BIT(1) /* output for SCL line */
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#define UNIPHIER_FI2C_BM_SCLS BIT(0) /* readback of SCL line */
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#define UNIPHIER_FI2C_NOISE 0x3c /* noise filter control */
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#define UNIPHIER_FI2C_TBC 0x40 /* TX byte count setting */
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#define UNIPHIER_FI2C_RBC 0x44 /* RX byte count setting */
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#define UNIPHIER_FI2C_TBCM 0x48 /* TX byte count monitor */
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#define UNIPHIER_FI2C_RBCM 0x4c /* RX byte count monitor */
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#define UNIPHIER_FI2C_BRST 0x50 /* bus reset */
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#define UNIPHIER_FI2C_BRST_FOEN BIT(1) /* normal operation */
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#define UNIPHIER_FI2C_BRST_RSCL BIT(0) /* release SCL */
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#define UNIPHIER_FI2C_INT_FAULTS \
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(UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL)
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#define UNIPHIER_FI2C_INT_STOP \
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(UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC)
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#define UNIPHIER_FI2C_RD BIT(0)
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#define UNIPHIER_FI2C_STOP BIT(1)
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#define UNIPHIER_FI2C_MANUAL_NACK BIT(2)
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#define UNIPHIER_FI2C_BYTE_WISE BIT(3)
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#define UNIPHIER_FI2C_DEFER_STOP_COMP BIT(4)
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#define UNIPHIER_FI2C_DEFAULT_SPEED 100000
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#define UNIPHIER_FI2C_MAX_SPEED 400000
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#define UNIPHIER_FI2C_FIFO_SIZE 8
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struct uniphier_fi2c_priv {
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struct completion comp;
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struct i2c_adapter adap;
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void __iomem *membase;
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struct clk *clk;
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unsigned int len;
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u8 *buf;
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u32 enabled_irqs;
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int error;
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unsigned int flags;
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unsigned int busy_cnt;
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};
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static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,
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bool first)
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{
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int fifo_space = UNIPHIER_FI2C_FIFO_SIZE;
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/*
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* TX-FIFO stores slave address in it for the first access.
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* Decrement the counter.
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*/
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if (first)
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fifo_space--;
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while (priv->len) {
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if (fifo_space-- <= 0)
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break;
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dev_dbg(&priv->adap.dev, "write data: %02x\n", *priv->buf);
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writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX);
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priv->len--;
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}
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}
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static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv *priv)
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{
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int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ?
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1 : UNIPHIER_FI2C_FIFO_SIZE;
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while (priv->len) {
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if (fifo_left-- <= 0)
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break;
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*priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX);
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dev_dbg(&priv->adap.dev, "read data: %02x\n", priv->buf[-1]);
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priv->len--;
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}
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}
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static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv *priv)
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{
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writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE);
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}
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static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv *priv)
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{
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writel(-1, priv->membase + UNIPHIER_FI2C_IC);
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}
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static void uniphier_fi2c_stop(struct uniphier_fi2c_priv *priv)
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{
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dev_dbg(&priv->adap.dev, "stop condition\n");
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priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP;
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uniphier_fi2c_set_irqs(priv);
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writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO,
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priv->membase + UNIPHIER_FI2C_CR);
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}
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static irqreturn_t uniphier_fi2c_interrupt(int irq, void *dev_id)
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{
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struct uniphier_fi2c_priv *priv = dev_id;
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u32 irq_status;
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irq_status = readl(priv->membase + UNIPHIER_FI2C_INT);
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dev_dbg(&priv->adap.dev,
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"interrupt: enabled_irqs=%04x, irq_status=%04x\n",
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priv->enabled_irqs, irq_status);
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if (irq_status & UNIPHIER_FI2C_INT_STOP)
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goto complete;
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if (unlikely(irq_status & UNIPHIER_FI2C_INT_AL)) {
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dev_dbg(&priv->adap.dev, "arbitration lost\n");
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priv->error = -EAGAIN;
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goto complete;
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}
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if (unlikely(irq_status & UNIPHIER_FI2C_INT_NA)) {
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dev_dbg(&priv->adap.dev, "could not get ACK\n");
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priv->error = -ENXIO;
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if (priv->flags & UNIPHIER_FI2C_RD) {
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/*
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* work around a hardware bug:
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* The receive-completed interrupt is never set even if
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* STOP condition is detected after the address phase
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* of read transaction fails to get ACK.
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* To avoid time-out error, we issue STOP here,
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* but do not wait for its completion.
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* It should be checked after exiting this handler.
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*/
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uniphier_fi2c_stop(priv);
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priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP;
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goto complete;
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}
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goto stop;
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}
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if (irq_status & UNIPHIER_FI2C_INT_TE) {
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if (!priv->len)
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goto data_done;
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uniphier_fi2c_fill_txfifo(priv, false);
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goto handled;
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}
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if (irq_status & (UNIPHIER_FI2C_INT_RF | UNIPHIER_FI2C_INT_RB)) {
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uniphier_fi2c_drain_rxfifo(priv);
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if (!priv->len)
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goto data_done;
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if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) {
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if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE &&
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!(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) {
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dev_dbg(&priv->adap.dev,
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"enable read byte count IRQ\n");
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priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB;
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uniphier_fi2c_set_irqs(priv);
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priv->flags |= UNIPHIER_FI2C_BYTE_WISE;
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}
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if (priv->len <= 1) {
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dev_dbg(&priv->adap.dev, "set NACK\n");
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writel(UNIPHIER_FI2C_CR_MST |
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UNIPHIER_FI2C_CR_NACK,
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priv->membase + UNIPHIER_FI2C_CR);
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}
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}
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goto handled;
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}
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return IRQ_NONE;
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data_done:
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if (priv->flags & UNIPHIER_FI2C_STOP) {
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stop:
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uniphier_fi2c_stop(priv);
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} else {
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complete:
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priv->enabled_irqs = 0;
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uniphier_fi2c_set_irqs(priv);
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complete(&priv->comp);
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}
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handled:
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uniphier_fi2c_clear_irqs(priv);
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return IRQ_HANDLED;
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}
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static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr)
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{
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priv->enabled_irqs |= UNIPHIER_FI2C_INT_TE;
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/* do not use TX byte counter */
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writel(0, priv->membase + UNIPHIER_FI2C_TBC);
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/* set slave address */
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writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1,
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priv->membase + UNIPHIER_FI2C_DTTX);
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/* first chunk of data */
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uniphier_fi2c_fill_txfifo(priv, true);
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}
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static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr)
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{
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priv->flags |= UNIPHIER_FI2C_RD;
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if (likely(priv->len < 256)) {
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/*
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* If possible, use RX byte counter.
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* It can automatically handle NACK for the last byte.
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*/
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writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC);
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priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF |
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UNIPHIER_FI2C_INT_RB;
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} else {
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/*
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* The byte counter can not count over 256. In this case,
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* do not use it at all. Drain data when FIFO gets full,
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* but treat the last portion as a special case.
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*/
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writel(0, priv->membase + UNIPHIER_FI2C_RBC);
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priv->flags |= UNIPHIER_FI2C_MANUAL_NACK;
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priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF;
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}
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/* set slave address with RD bit */
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writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1,
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priv->membase + UNIPHIER_FI2C_DTTX);
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}
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static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv)
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{
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writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST);
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}
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static void uniphier_fi2c_prepare_operation(struct uniphier_fi2c_priv *priv)
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{
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writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL,
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priv->membase + UNIPHIER_FI2C_BRST);
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}
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static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv)
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{
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uniphier_fi2c_reset(priv);
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i2c_recover_bus(&priv->adap);
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}
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static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap,
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struct i2c_msg *msg, bool stop)
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{
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struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
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bool is_read = msg->flags & I2C_M_RD;
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unsigned long time_left;
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dev_dbg(&adap->dev, "%s: addr=0x%02x, len=%d, stop=%d\n",
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is_read ? "receive" : "transmit", msg->addr, msg->len, stop);
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priv->len = msg->len;
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priv->buf = msg->buf;
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priv->enabled_irqs = UNIPHIER_FI2C_INT_FAULTS;
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priv->error = 0;
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priv->flags = 0;
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if (stop)
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priv->flags |= UNIPHIER_FI2C_STOP;
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reinit_completion(&priv->comp);
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uniphier_fi2c_clear_irqs(priv);
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writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST,
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priv->membase + UNIPHIER_FI2C_RST); /* reset TX/RX FIFO */
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if (is_read)
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uniphier_fi2c_rx_init(priv, msg->addr);
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else
|
||||
uniphier_fi2c_tx_init(priv, msg->addr);
|
||||
|
||||
uniphier_fi2c_set_irqs(priv);
|
||||
|
||||
dev_dbg(&adap->dev, "start condition\n");
|
||||
writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA,
|
||||
priv->membase + UNIPHIER_FI2C_CR);
|
||||
|
||||
time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
|
||||
if (!time_left) {
|
||||
dev_err(&adap->dev, "transaction timeout.\n");
|
||||
uniphier_fi2c_recover(priv);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
dev_dbg(&adap->dev, "complete\n");
|
||||
|
||||
if (unlikely(priv->flags & UNIPHIER_FI2C_DEFER_STOP_COMP)) {
|
||||
u32 status = readl(priv->membase + UNIPHIER_FI2C_SR);
|
||||
|
||||
if (!(status & UNIPHIER_FI2C_SR_STS) ||
|
||||
status & UNIPHIER_FI2C_SR_BB) {
|
||||
dev_err(&adap->dev,
|
||||
"stop condition was not completed.\n");
|
||||
uniphier_fi2c_recover(priv);
|
||||
return -EBUSY;
|
||||
}
|
||||
}
|
||||
|
||||
return priv->error;
|
||||
}
|
||||
|
||||
static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap)
|
||||
{
|
||||
struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
|
||||
|
||||
if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) {
|
||||
if (priv->busy_cnt++ > 3) {
|
||||
/*
|
||||
* If bus busy continues too long, it is probably
|
||||
* in a wrong state. Try bus recovery.
|
||||
*/
|
||||
uniphier_fi2c_recover(priv);
|
||||
priv->busy_cnt = 0;
|
||||
}
|
||||
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
priv->busy_cnt = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
|
||||
struct i2c_msg *msgs, int num)
|
||||
{
|
||||
struct i2c_msg *msg, *emsg = msgs + num;
|
||||
int ret;
|
||||
|
||||
ret = uniphier_fi2c_check_bus_busy(adap);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (msg = msgs; msg < emsg; msg++) {
|
||||
/* If next message is read, skip the stop condition */
|
||||
bool stop = !(msg + 1 < emsg && msg[1].flags & I2C_M_RD);
|
||||
/* but, force it if I2C_M_STOP is set */
|
||||
if (msg->flags & I2C_M_STOP)
|
||||
stop = true;
|
||||
|
||||
ret = uniphier_fi2c_master_xfer_one(adap, msg, stop);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return num;
|
||||
}
|
||||
|
||||
static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm uniphier_fi2c_algo = {
|
||||
.master_xfer = uniphier_fi2c_master_xfer,
|
||||
.functionality = uniphier_fi2c_functionality,
|
||||
};
|
||||
|
||||
static int uniphier_fi2c_get_scl(struct i2c_adapter *adap)
|
||||
{
|
||||
struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
|
||||
|
||||
return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
|
||||
UNIPHIER_FI2C_BM_SCLS);
|
||||
}
|
||||
|
||||
static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val)
|
||||
{
|
||||
struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
|
||||
|
||||
writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0,
|
||||
priv->membase + UNIPHIER_FI2C_BRST);
|
||||
}
|
||||
|
||||
static int uniphier_fi2c_get_sda(struct i2c_adapter *adap)
|
||||
{
|
||||
struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
|
||||
|
||||
return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
|
||||
UNIPHIER_FI2C_BM_SDAS);
|
||||
}
|
||||
|
||||
static void uniphier_fi2c_unprepare_recovery(struct i2c_adapter *adap)
|
||||
{
|
||||
uniphier_fi2c_prepare_operation(i2c_get_adapdata(adap));
|
||||
}
|
||||
|
||||
static struct i2c_bus_recovery_info uniphier_fi2c_bus_recovery_info = {
|
||||
.recover_bus = i2c_generic_scl_recovery,
|
||||
.get_scl = uniphier_fi2c_get_scl,
|
||||
.set_scl = uniphier_fi2c_set_scl,
|
||||
.get_sda = uniphier_fi2c_get_sda,
|
||||
.unprepare_recovery = uniphier_fi2c_unprepare_recovery,
|
||||
};
|
||||
|
||||
static int uniphier_fi2c_clk_init(struct device *dev,
|
||||
struct uniphier_fi2c_priv *priv)
|
||||
{
|
||||
struct device_node *np = dev->of_node;
|
||||
unsigned long clk_rate;
|
||||
u32 bus_speed, clk_count;
|
||||
int ret;
|
||||
|
||||
if (of_property_read_u32(np, "clock-frequency", &bus_speed))
|
||||
bus_speed = UNIPHIER_FI2C_DEFAULT_SPEED;
|
||||
|
||||
if (bus_speed > UNIPHIER_FI2C_MAX_SPEED)
|
||||
bus_speed = UNIPHIER_FI2C_MAX_SPEED;
|
||||
|
||||
/* Get input clk rate through clk driver */
|
||||
priv->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(priv->clk)) {
|
||||
dev_err(dev, "failed to get clock\n");
|
||||
return PTR_ERR(priv->clk);
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(priv->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
clk_rate = clk_get_rate(priv->clk);
|
||||
|
||||
uniphier_fi2c_reset(priv);
|
||||
|
||||
clk_count = clk_rate / bus_speed;
|
||||
|
||||
writel(clk_count, priv->membase + UNIPHIER_FI2C_CYC);
|
||||
writel(clk_count / 2, priv->membase + UNIPHIER_FI2C_LCTL);
|
||||
writel(clk_count / 2, priv->membase + UNIPHIER_FI2C_SSUT);
|
||||
writel(clk_count / 16, priv->membase + UNIPHIER_FI2C_DSUT);
|
||||
|
||||
uniphier_fi2c_prepare_operation(priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int uniphier_fi2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct uniphier_fi2c_priv *priv;
|
||||
struct resource *regs;
|
||||
int irq;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
priv->membase = devm_ioremap_resource(dev, regs);
|
||||
if (IS_ERR(priv->membase))
|
||||
return PTR_ERR(priv->membase);
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(dev, "failed to get IRQ number");
|
||||
return irq;
|
||||
}
|
||||
|
||||
init_completion(&priv->comp);
|
||||
priv->adap.owner = THIS_MODULE;
|
||||
priv->adap.algo = &uniphier_fi2c_algo;
|
||||
priv->adap.dev.parent = dev;
|
||||
priv->adap.dev.of_node = dev->of_node;
|
||||
strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));
|
||||
priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info;
|
||||
i2c_set_adapdata(&priv->adap, priv);
|
||||
platform_set_drvdata(pdev, priv);
|
||||
|
||||
ret = uniphier_fi2c_clk_init(dev, priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0,
|
||||
pdev->name, priv);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to request irq %d\n", irq);
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = i2c_add_adapter(&priv->adap);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to add I2C adapter\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
err:
|
||||
if (ret)
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int uniphier_fi2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct uniphier_fi2c_priv *priv = platform_get_drvdata(pdev);
|
||||
|
||||
i2c_del_adapter(&priv->adap);
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id uniphier_fi2c_match[] = {
|
||||
{ .compatible = "socionext,uniphier-fi2c" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, uniphier_fi2c_match);
|
||||
|
||||
static struct platform_driver uniphier_fi2c_drv = {
|
||||
.probe = uniphier_fi2c_probe,
|
||||
.remove = uniphier_fi2c_remove,
|
||||
.driver = {
|
||||
.name = "uniphier-fi2c",
|
||||
.of_match_table = uniphier_fi2c_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(uniphier_fi2c_drv);
|
||||
|
||||
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
|
||||
MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue