mirror of https://gitee.com/openkylin/linux.git
for 3.16 merge window
Bunch of fixes and a new driver for Exynos5 USB 3.0 PHY. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJTdggGAAoJEA5ceFyATYLZZXEQAI3aOHMET9KP6f34vOWRfZvv tbcU+hHKkzPAqZaRjX1DErMHfMW09Lcd0K2xSq6UK9xoD9QrYdxl33KaOTHJ3cGC ioSKBXFbx1BNXDLezl7gWPRsdYLWAJLzzR+3Xh/XGcLMBI0Scxka+iOm5i/2kH6G VwMJ/RAhbVVlTxiOzhdH8FUfdIcsv4n07BfYtHIa2UOw+kiLl1bjNtn2MJisbkO/ N5doz7gy5CBXCGo8g6P88H2NrHY2/VPYUiog+uGgq6punncvh9Jrt+veZFm+9Biv HPE1/l/q6XvJpy82qB1wyk+ERZTSlZP0f/GZhCtysa5NX16efnbdVA0kAcMF3Cgc V6hDx1PuY1GjQO9MobIo6RE23RQfy+ktKQ6maxkJDrqM2v+oj6dr3q/R1gpnfjz3 Cs3ndtPYEEA+1TJRgvLr9M+DEB4SPeZYCRil4JMsEr0upMlXo81t12Tvk8/QIpO0 hmZPgfPnKkuF8AnYrQkM3qAawzbaVsBAtnJGfExmPyFMOrtjS0VgG0TPDmj7G6Hx PGovqPokEFj2F+HAhQcQynx3RjUFcyboDpY4uHNYqL1h3ZuqOpoGwbjI1cjUEHm4 ExKF4MpePRwHCSxzcVrpoqKeHGkcAhKPZc1BA4Cul1jv0aNS6HEs8Nylf7eUsX0O 5b34Zk0GXHNfP6xnQiHi =gwmY -----END PGP SIGNATURE----- Merge tag 'for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: for 3.16 merge window Bunch of fixes and a new driver for Exynos5 USB 3.0 PHY.
This commit is contained in:
Greg Kroah-Hartman
commit
6aba2ae764
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@ -114,3 +114,50 @@ Example:
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compatible = "samsung,exynos-sataphy-i2c";
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reg = <0x38>;
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};
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Samsung Exynos5 SoC series USB DRD PHY controller
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--------------------------------------------------
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Required properties:
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- compatible : Should be set to one of the following supported values:
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- "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
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- "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
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- reg : Register offset and length of USB DRD PHY register set;
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- clocks: Clock IDs array as required by the controller
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- clock-names: names of clocks correseponding to IDs in the clock property;
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Required clocks:
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- phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
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used for register access.
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- ref: PHY's reference clock (usually crystal clock), used for
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PHY operations, associated by phy name. It is used to
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determine bit values for clock settings register.
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For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
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- samsung,pmu-syscon: phandle for PMU system controller interface, used to
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control pmu registers for power isolation.
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- #phy-cells : from the generic PHY bindings, must be 1;
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For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
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compatible PHYs, the second cell in the PHY specifier identifies the
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PHY id, which is interpreted as follows:
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0 - UTMI+ type phy,
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1 - PIPE3 type phy,
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Example:
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usbdrd_phy: usbphy@12100000 {
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compatible = "samsung,exynos5250-usbdrd-phy";
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reg = <0x12100000 0x100>;
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clocks = <&clock 286>, <&clock 1>;
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clock-names = "phy", "ref";
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samsung,pmu-syscon = <&pmu_system_controller>;
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#phy-cells = <1>;
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};
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- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
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'usbdrd_phy' nodes should have numbered alias in the aliases node,
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in the form of usbdrdphyN, N = 0, 1... (depending on number of
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controllers).
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Example:
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aliases {
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usbdrdphy0 = &usb3_phy0;
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usbdrdphy1 = &usb3_phy1;
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};
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@ -2,15 +2,26 @@ Allwinner sun4i USB PHY
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-----------------------
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Required properties:
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- compatible : should be one of "allwinner,sun4i-a10-usb-phy",
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"allwinner,sun5i-a13-usb-phy" or "allwinner,sun7i-a20-usb-phy"
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- compatible : should be one of
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* allwinner,sun4i-a10-usb-phy
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* allwinner,sun5i-a13-usb-phy
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* allwinner,sun6i-a31-usb-phy
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* allwinner,sun7i-a20-usb-phy
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- reg : a list of offset + length pairs
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- reg-names : "phy_ctrl", "pmu1" and for sun4i or sun7i "pmu2"
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- reg-names :
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* "phy_ctrl"
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* "pmu1"
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* "pmu2" for sun4i, sun6i or sun7i
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- #phy-cells : from the generic phy bindings, must be 1
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- clocks : phandle + clock specifier for the phy clock
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- clock-names : "usb_phy"
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- clocks : phandle + clock specifier for the phy clocks
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- clock-names :
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* "usb_phy" for sun4i, sun5i or sun7i
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* "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
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- resets : a list of phandle + reset specifier pairs
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- reset-names : "usb0_reset", "usb1_reset" and for sun4i or sun7i "usb2_reset"
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- reset-names :
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* "usb0_reset"
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* "usb1_reset"
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* "usb2_reset" for sun4i, sun6i or sun7i
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Example:
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usbphy: phy@0x01c13400 {
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@ -32,6 +32,11 @@ Required properties:
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- reg : Address and length of the register set for the device.
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- #phy-cells: determine the number of cells that should be given in the
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phandle while referencing this phy.
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- clocks: a list of phandles and clock-specifier pairs, one for each entry in
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clock-names.
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- clock-names: should include:
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* "wkupclk" - wakeup clock.
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* "refclk" - reference clock (optional).
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Optional properties:
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- ctrl-module : phandle of the control module used by PHY driver to power on
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@ -44,6 +49,8 @@ usb2phy@4a0ad080 {
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reg = <0x4a0ad080 0x58>;
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ctrl-module = <&omap_control_usb>;
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#phy-cells = <0>;
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clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
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clock-names = "wkupclk", "refclk";
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};
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TI PIPE3 PHY
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@ -89,8 +89,8 @@ config PHY_EXYNOS_DP_VIDEO
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config BCM_KONA_USB2_PHY
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tristate "Broadcom Kona USB2 PHY Driver"
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depends on GENERIC_PHY
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depends on HAS_IOMEM
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select GENERIC_PHY
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help
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Enable this to support the Broadcom Kona USB 2.0 PHY.
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@ -160,6 +160,17 @@ config PHY_EXYNOS5250_USB2
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particular SoC is compiled in the driver. In case of Exynos 5250 four
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phys are available - device, host, HSIC0 and HSIC.
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config PHY_EXYNOS5_USBDRD
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tristate "Exynos5 SoC series USB DRD PHY driver"
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depends on ARCH_EXYNOS5 && OF
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depends on HAS_IOMEM
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select GENERIC_PHY
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select MFD_SYSCON
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help
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Enable USB DRD PHY support for Exynos 5 SoC series.
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This driver provides PHY interface for USB 3.0 DRD controller
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present on Exynos5 SoC series.
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config PHY_XGENE
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tristate "APM X-Gene 15Gbps PHY support"
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depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)
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@ -18,4 +18,5 @@ phy-exynos-usb2-y += phy-samsung-usb2.o
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phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
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phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
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phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
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obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
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obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
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@ -101,7 +101,7 @@ static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
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{
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struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
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if (WARN_ON(args->args[0] > EXYNOS_MIPI_PHYS_NUM))
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if (WARN_ON(args->args[0] >= EXYNOS_MIPI_PHYS_NUM))
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return ERR_PTR(-ENODEV);
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return state->phys[args->args[0]].phy;
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@ -0,0 +1,676 @@
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/*
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* Samsung EXYNOS5 SoC series USB DRD PHY driver
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*
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* Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
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*
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* Copyright (C) 2014 Samsung Electronics Co., Ltd.
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* Author: Vivek Gautam <gautam.vivek@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/mutex.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/exynos5-pmu.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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/* Exynos USB PHY registers */
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#define EXYNOS5_FSEL_9MHZ6 0x0
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#define EXYNOS5_FSEL_10MHZ 0x1
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#define EXYNOS5_FSEL_12MHZ 0x2
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#define EXYNOS5_FSEL_19MHZ2 0x3
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#define EXYNOS5_FSEL_20MHZ 0x4
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#define EXYNOS5_FSEL_24MHZ 0x5
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#define EXYNOS5_FSEL_50MHZ 0x7
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/* EXYNOS5: USB 3.0 DRD PHY registers */
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#define EXYNOS5_DRD_LINKSYSTEM 0x04
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#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
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#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
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#define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27)
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#define EXYNOS5_DRD_PHYUTMI 0x08
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#define PHYUTMI_OTGDISABLE BIT(6)
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#define PHYUTMI_FORCESUSPEND BIT(1)
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#define PHYUTMI_FORCESLEEP BIT(0)
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#define EXYNOS5_DRD_PHYPIPE 0x0c
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#define EXYNOS5_DRD_PHYCLKRST 0x10
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#define PHYCLKRST_EN_UTMISUSPEND BIT(31)
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#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
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#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
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#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
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#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
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#define PHYCLKRST_SSC_EN BIT(20)
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#define PHYCLKRST_REF_SSP_EN BIT(19)
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#define PHYCLKRST_REF_CLKDIV2 BIT(18)
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#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x32 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
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#define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5)
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#define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8)
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#define PHYCLKRST_FSEL(_x) ((_x) << 5)
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#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
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#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
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#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
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#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
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#define PHYCLKRST_RETENABLEN BIT(4)
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#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
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#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
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#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
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#define PHYCLKRST_PORTRESET BIT(1)
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#define PHYCLKRST_COMMONONN BIT(0)
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#define EXYNOS5_DRD_PHYREG0 0x14
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#define EXYNOS5_DRD_PHYREG1 0x18
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#define EXYNOS5_DRD_PHYPARAM0 0x1c
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#define PHYPARAM0_REF_USE_PAD BIT(31)
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#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
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#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
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#define EXYNOS5_DRD_PHYPARAM1 0x20
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#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
|
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#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
|
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|
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#define EXYNOS5_DRD_PHYTERM 0x24
|
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|
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#define EXYNOS5_DRD_PHYTEST 0x28
|
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|
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#define PHYTEST_POWERDOWN_SSP BIT(3)
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#define PHYTEST_POWERDOWN_HSP BIT(2)
|
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|
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#define EXYNOS5_DRD_PHYADP 0x2c
|
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|
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#define EXYNOS5_DRD_PHYUTMICLKSEL 0x30
|
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|
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#define PHYUTMICLKSEL_UTMI_CLKSEL BIT(2)
|
||||
|
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#define EXYNOS5_DRD_PHYRESUME 0x34
|
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#define EXYNOS5_DRD_LINKPORT 0x44
|
||||
|
||||
#define KHZ 1000
|
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#define MHZ (KHZ * KHZ)
|
||||
|
||||
enum exynos5_usbdrd_phy_id {
|
||||
EXYNOS5_DRDPHY_UTMI,
|
||||
EXYNOS5_DRDPHY_PIPE3,
|
||||
EXYNOS5_DRDPHYS_NUM,
|
||||
};
|
||||
|
||||
struct phy_usb_instance;
|
||||
struct exynos5_usbdrd_phy;
|
||||
|
||||
struct exynos5_usbdrd_phy_config {
|
||||
u32 id;
|
||||
void (*phy_isol)(struct phy_usb_instance *inst, u32 on);
|
||||
void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd);
|
||||
unsigned int (*set_refclk)(struct phy_usb_instance *inst);
|
||||
};
|
||||
|
||||
struct exynos5_usbdrd_phy_drvdata {
|
||||
const struct exynos5_usbdrd_phy_config *phy_cfg;
|
||||
u32 pmu_offset_usbdrd0_phy;
|
||||
u32 pmu_offset_usbdrd1_phy;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
|
||||
* @dev: pointer to device instance of this platform device
|
||||
* @reg_phy: usb phy controller register memory base
|
||||
* @clk: phy clock for register access
|
||||
* @drv_data: pointer to SoC level driver data structure
|
||||
* @phys[]: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
|
||||
* instances each with its 'phy' and 'phy_cfg'.
|
||||
* @extrefclk: frequency select settings when using 'separate
|
||||
* reference clocks' for SS and HS operations
|
||||
* @ref_clk: reference clock to PHY block from which PHY's
|
||||
* operational clocks are derived
|
||||
* @ref_rate: rate of above reference clock
|
||||
*/
|
||||
struct exynos5_usbdrd_phy {
|
||||
struct device *dev;
|
||||
void __iomem *reg_phy;
|
||||
struct clk *clk;
|
||||
const struct exynos5_usbdrd_phy_drvdata *drv_data;
|
||||
struct phy_usb_instance {
|
||||
struct phy *phy;
|
||||
u32 index;
|
||||
struct regmap *reg_pmu;
|
||||
u32 pmu_offset;
|
||||
const struct exynos5_usbdrd_phy_config *phy_cfg;
|
||||
} phys[EXYNOS5_DRDPHYS_NUM];
|
||||
u32 extrefclk;
|
||||
struct clk *ref_clk;
|
||||
struct regulator *vbus;
|
||||
};
|
||||
|
||||
static inline
|
||||
struct exynos5_usbdrd_phy *to_usbdrd_phy(struct phy_usb_instance *inst)
|
||||
{
|
||||
return container_of((inst), struct exynos5_usbdrd_phy,
|
||||
phys[(inst)->index]);
|
||||
}
|
||||
|
||||
/*
|
||||
* exynos5_rate_to_clk() converts the supplied clock rate to the value that
|
||||
* can be written to the phy register.
|
||||
*/
|
||||
static unsigned int exynos5_rate_to_clk(unsigned long rate, u32 *reg)
|
||||
{
|
||||
/* EXYNOS5_FSEL_MASK */
|
||||
|
||||
switch (rate) {
|
||||
case 9600 * KHZ:
|
||||
*reg = EXYNOS5_FSEL_9MHZ6;
|
||||
break;
|
||||
case 10 * MHZ:
|
||||
*reg = EXYNOS5_FSEL_10MHZ;
|
||||
break;
|
||||
case 12 * MHZ:
|
||||
*reg = EXYNOS5_FSEL_12MHZ;
|
||||
break;
|
||||
case 19200 * KHZ:
|
||||
*reg = EXYNOS5_FSEL_19MHZ2;
|
||||
break;
|
||||
case 20 * MHZ:
|
||||
*reg = EXYNOS5_FSEL_20MHZ;
|
||||
break;
|
||||
case 24 * MHZ:
|
||||
*reg = EXYNOS5_FSEL_24MHZ;
|
||||
break;
|
||||
case 50 * MHZ:
|
||||
*reg = EXYNOS5_FSEL_50MHZ;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst,
|
||||
unsigned int on)
|
||||
{
|
||||
unsigned int val;
|
||||
|
||||
if (!inst->reg_pmu)
|
||||
return;
|
||||
|
||||
val = on ? 0 : EXYNOS5_PHY_ENABLE;
|
||||
|
||||
regmap_update_bits(inst->reg_pmu, inst->pmu_offset,
|
||||
EXYNOS5_PHY_ENABLE, val);
|
||||
}
|
||||
|
||||
/*
|
||||
* Sets the pipe3 phy's clk as EXTREFCLK (XXTI) which is internal clock
|
||||
* from clock core. Further sets multiplier values and spread spectrum
|
||||
* clock settings for SuperSpeed operations.
|
||||
*/
|
||||
static unsigned int
|
||||
exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst)
|
||||
{
|
||||
static u32 reg;
|
||||
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
|
||||
|
||||
/* restore any previous reference clock settings */
|
||||
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
|
||||
|
||||
/* Use EXTREFCLK as ref clock */
|
||||
reg &= ~PHYCLKRST_REFCLKSEL_MASK;
|
||||
reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK;
|
||||
|
||||
/* FSEL settings corresponding to reference clock */
|
||||
reg &= ~PHYCLKRST_FSEL_PIPE_MASK |
|
||||
PHYCLKRST_MPLL_MULTIPLIER_MASK |
|
||||
PHYCLKRST_SSC_REFCLKSEL_MASK;
|
||||
switch (phy_drd->extrefclk) {
|
||||
case EXYNOS5_FSEL_50MHZ:
|
||||
reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
|
||||
PHYCLKRST_SSC_REFCLKSEL(0x00));
|
||||
break;
|
||||
case EXYNOS5_FSEL_24MHZ:
|
||||
reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
|
||||
PHYCLKRST_SSC_REFCLKSEL(0x88));
|
||||
break;
|
||||
case EXYNOS5_FSEL_20MHZ:
|
||||
reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
|
||||
PHYCLKRST_SSC_REFCLKSEL(0x00));
|
||||
break;
|
||||
case EXYNOS5_FSEL_19MHZ2:
|
||||
reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
|
||||
PHYCLKRST_SSC_REFCLKSEL(0x88));
|
||||
break;
|
||||
default:
|
||||
dev_dbg(phy_drd->dev, "unsupported ref clk\n");
|
||||
break;
|
||||
}
|
||||
|
||||
return reg;
|
||||
}
|
||||
|
||||
/*
|
||||
* Sets the utmi phy's clk as EXTREFCLK (XXTI) which is internal clock
|
||||
* from clock core. Further sets the FSEL values for HighSpeed operations.
|
||||
*/
|
||||
static unsigned int
|
||||
exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst)
|
||||
{
|
||||
static u32 reg;
|
||||
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
|
||||
|
||||
/* restore any previous reference clock settings */
|
||||
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
|
||||
|
||||
reg &= ~PHYCLKRST_REFCLKSEL_MASK;
|
||||
reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK;
|
||||
|
||||
reg &= ~PHYCLKRST_FSEL_UTMI_MASK |
|
||||
PHYCLKRST_MPLL_MULTIPLIER_MASK |
|
||||
PHYCLKRST_SSC_REFCLKSEL_MASK;
|
||||
reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);
|
||||
|
||||
return reg;
|
||||
}
|
||||
|
||||
static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
|
||||
/* Set Tx De-Emphasis level */
|
||||
reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
|
||||
reg |= PHYPARAM1_PCS_TXDEEMPH;
|
||||
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
|
||||
|
||||
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
|
||||
reg &= ~PHYTEST_POWERDOWN_SSP;
|
||||
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
|
||||
}
|
||||
|
||||
static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
|
||||
/* Set Loss-of-Signal Detector sensitivity */
|
||||
reg &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
|
||||
reg |= PHYPARAM0_REF_LOSLEVEL;
|
||||
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
|
||||
|
||||
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
|
||||
/* Set Tx De-Emphasis level */
|
||||
reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
|
||||
reg |= PHYPARAM1_PCS_TXDEEMPH;
|
||||
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
|
||||
|
||||
/* UTMI Power Control */
|
||||
writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
|
||||
|
||||
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
|
||||
reg &= ~PHYTEST_POWERDOWN_HSP;
|
||||
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
|
||||
}
|
||||
|
||||
static int exynos5_usbdrd_phy_init(struct phy *phy)
|
||||
{
|
||||
int ret;
|
||||
u32 reg;
|
||||
struct phy_usb_instance *inst = phy_get_drvdata(phy);
|
||||
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
|
||||
|
||||
ret = clk_prepare_enable(phy_drd->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Reset USB 3.0 PHY */
|
||||
writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
|
||||
writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME);
|
||||
|
||||
/*
|
||||
* Setting the Frame length Adj value[6:1] to default 0x20
|
||||
* See xHCI 1.0 spec, 5.2.4
|
||||
*/
|
||||
reg = LINKSYSTEM_XHCI_VERSION_CONTROL |
|
||||
LINKSYSTEM_FLADJ(0x20);
|
||||
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
|
||||
|
||||
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
|
||||
/* Select PHY CLK source */
|
||||
reg &= ~PHYPARAM0_REF_USE_PAD;
|
||||
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
|
||||
|
||||
/* This bit must be set for both HS and SS operations */
|
||||
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
|
||||
reg |= PHYUTMICLKSEL_UTMI_CLKSEL;
|
||||
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
|
||||
|
||||
/* UTMI or PIPE3 specific init */
|
||||
inst->phy_cfg->phy_init(phy_drd);
|
||||
|
||||
/* reference clock settings */
|
||||
reg = inst->phy_cfg->set_refclk(inst);
|
||||
|
||||
/* Digital power supply in normal operating mode */
|
||||
reg |= PHYCLKRST_RETENABLEN |
|
||||
/* Enable ref clock for SS function */
|
||||
PHYCLKRST_REF_SSP_EN |
|
||||
/* Enable spread spectrum */
|
||||
PHYCLKRST_SSC_EN |
|
||||
/* Power down HS Bias and PLL blocks in suspend mode */
|
||||
PHYCLKRST_COMMONONN |
|
||||
/* Reset the port */
|
||||
PHYCLKRST_PORTRESET;
|
||||
|
||||
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
|
||||
|
||||
udelay(10);
|
||||
|
||||
reg &= ~PHYCLKRST_PORTRESET;
|
||||
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
|
||||
|
||||
clk_disable_unprepare(phy_drd->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int exynos5_usbdrd_phy_exit(struct phy *phy)
|
||||
{
|
||||
int ret;
|
||||
u32 reg;
|
||||
struct phy_usb_instance *inst = phy_get_drvdata(phy);
|
||||
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
|
||||
|
||||
ret = clk_prepare_enable(phy_drd->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
reg = PHYUTMI_OTGDISABLE |
|
||||
PHYUTMI_FORCESUSPEND |
|
||||
PHYUTMI_FORCESLEEP;
|
||||
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
|
||||
|
||||
/* Resetting the PHYCLKRST enable bits to reduce leakage current */
|
||||
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
|
||||
reg &= ~(PHYCLKRST_REF_SSP_EN |
|
||||
PHYCLKRST_SSC_EN |
|
||||
PHYCLKRST_COMMONONN);
|
||||
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
|
||||
|
||||
/* Control PHYTEST to remove leakage current */
|
||||
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
|
||||
reg |= PHYTEST_POWERDOWN_SSP |
|
||||
PHYTEST_POWERDOWN_HSP;
|
||||
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
|
||||
|
||||
clk_disable_unprepare(phy_drd->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int exynos5_usbdrd_phy_power_on(struct phy *phy)
|
||||
{
|
||||
int ret;
|
||||
struct phy_usb_instance *inst = phy_get_drvdata(phy);
|
||||
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
|
||||
|
||||
dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n");
|
||||
|
||||
clk_prepare_enable(phy_drd->ref_clk);
|
||||
|
||||
/* Enable VBUS supply */
|
||||
if (phy_drd->vbus) {
|
||||
ret = regulator_enable(phy_drd->vbus);
|
||||
if (ret) {
|
||||
dev_err(phy_drd->dev, "Failed to enable VBUS supply\n");
|
||||
goto fail_vbus;
|
||||
}
|
||||
}
|
||||
|
||||
/* Power-on PHY*/
|
||||
inst->phy_cfg->phy_isol(inst, 0);
|
||||
|
||||
return 0;
|
||||
|
||||
fail_vbus:
|
||||
clk_disable_unprepare(phy_drd->ref_clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int exynos5_usbdrd_phy_power_off(struct phy *phy)
|
||||
{
|
||||
struct phy_usb_instance *inst = phy_get_drvdata(phy);
|
||||
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
|
||||
|
||||
dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n");
|
||||
|
||||
/* Power-off the PHY */
|
||||
inst->phy_cfg->phy_isol(inst, 1);
|
||||
|
||||
/* Disable VBUS supply */
|
||||
if (phy_drd->vbus)
|
||||
regulator_disable(phy_drd->vbus);
|
||||
|
||||
clk_disable_unprepare(phy_drd->ref_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,
|
||||
struct of_phandle_args *args)
|
||||
{
|
||||
struct exynos5_usbdrd_phy *phy_drd = dev_get_drvdata(dev);
|
||||
|
||||
if (WARN_ON(args->args[0] > EXYNOS5_DRDPHYS_NUM))
|
||||
return ERR_PTR(-ENODEV);
|
||||
|
||||
return phy_drd->phys[args->args[0]].phy;
|
||||
}
|
||||
|
||||
static struct phy_ops exynos5_usbdrd_phy_ops = {
|
||||
.init = exynos5_usbdrd_phy_init,
|
||||
.exit = exynos5_usbdrd_phy_exit,
|
||||
.power_on = exynos5_usbdrd_phy_power_on,
|
||||
.power_off = exynos5_usbdrd_phy_power_off,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = {
|
||||
{
|
||||
.id = EXYNOS5_DRDPHY_UTMI,
|
||||
.phy_isol = exynos5_usbdrd_phy_isol,
|
||||
.phy_init = exynos5_usbdrd_utmi_init,
|
||||
.set_refclk = exynos5_usbdrd_utmi_set_refclk,
|
||||
},
|
||||
{
|
||||
.id = EXYNOS5_DRDPHY_PIPE3,
|
||||
.phy_isol = exynos5_usbdrd_phy_isol,
|
||||
.phy_init = exynos5_usbdrd_pipe3_init,
|
||||
.set_refclk = exynos5_usbdrd_pipe3_set_refclk,
|
||||
},
|
||||
};
|
||||
|
||||
const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
|
||||
.phy_cfg = phy_cfg_exynos5,
|
||||
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
|
||||
.pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL,
|
||||
};
|
||||
|
||||
const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = {
|
||||
.phy_cfg = phy_cfg_exynos5,
|
||||
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
|
||||
};
|
||||
|
||||
static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
|
||||
{
|
||||
.compatible = "samsung,exynos5250-usbdrd-phy",
|
||||
.data = &exynos5250_usbdrd_phy
|
||||
}, {
|
||||
.compatible = "samsung,exynos5420-usbdrd-phy",
|
||||
.data = &exynos5420_usbdrd_phy
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->of_node;
|
||||
struct exynos5_usbdrd_phy *phy_drd;
|
||||
struct phy_provider *phy_provider;
|
||||
struct resource *res;
|
||||
const struct of_device_id *match;
|
||||
const struct exynos5_usbdrd_phy_drvdata *drv_data;
|
||||
struct regmap *reg_pmu;
|
||||
u32 pmu_offset;
|
||||
unsigned long ref_rate;
|
||||
int i, ret;
|
||||
int channel;
|
||||
|
||||
phy_drd = devm_kzalloc(dev, sizeof(*phy_drd), GFP_KERNEL);
|
||||
if (!phy_drd)
|
||||
return -ENOMEM;
|
||||
|
||||
dev_set_drvdata(dev, phy_drd);
|
||||
phy_drd->dev = dev;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
phy_drd->reg_phy = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(phy_drd->reg_phy))
|
||||
return PTR_ERR(phy_drd->reg_phy);
|
||||
|
||||
match = of_match_node(exynos5_usbdrd_phy_of_match, pdev->dev.of_node);
|
||||
|
||||
drv_data = match->data;
|
||||
phy_drd->drv_data = drv_data;
|
||||
|
||||
phy_drd->clk = devm_clk_get(dev, "phy");
|
||||
if (IS_ERR(phy_drd->clk)) {
|
||||
dev_err(dev, "Failed to get clock of phy controller\n");
|
||||
return PTR_ERR(phy_drd->clk);
|
||||
}
|
||||
|
||||
phy_drd->ref_clk = devm_clk_get(dev, "ref");
|
||||
if (IS_ERR(phy_drd->ref_clk)) {
|
||||
dev_err(dev, "Failed to get reference clock of usbdrd phy\n");
|
||||
return PTR_ERR(phy_drd->ref_clk);
|
||||
}
|
||||
ref_rate = clk_get_rate(phy_drd->ref_clk);
|
||||
|
||||
ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
|
||||
if (ret) {
|
||||
dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n",
|
||||
ref_rate);
|
||||
return ret;
|
||||
}
|
||||
|
||||
reg_pmu = syscon_regmap_lookup_by_phandle(dev->of_node,
|
||||
"samsung,pmu-syscon");
|
||||
if (IS_ERR(reg_pmu)) {
|
||||
dev_err(dev, "Failed to lookup PMU regmap\n");
|
||||
return PTR_ERR(reg_pmu);
|
||||
}
|
||||
|
||||
/*
|
||||
* Exynos5420 SoC has multiple channels for USB 3.0 PHY, with
|
||||
* each having separate power control registers.
|
||||
* 'channel' facilitates to set such registers.
|
||||
*/
|
||||
channel = of_alias_get_id(node, "usbdrdphy");
|
||||
if (channel < 0)
|
||||
dev_dbg(dev, "Not a multi-controller usbdrd phy\n");
|
||||
|
||||
switch (channel) {
|
||||
case 1:
|
||||
pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd1_phy;
|
||||
break;
|
||||
case 0:
|
||||
default:
|
||||
pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd0_phy;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Get Vbus regulator */
|
||||
phy_drd->vbus = devm_regulator_get(dev, "vbus");
|
||||
if (IS_ERR(phy_drd->vbus)) {
|
||||
ret = PTR_ERR(phy_drd->vbus);
|
||||
if (ret == -EPROBE_DEFER)
|
||||
return ret;
|
||||
|
||||
dev_warn(dev, "Failed to get VBUS supply regulator\n");
|
||||
phy_drd->vbus = NULL;
|
||||
}
|
||||
|
||||
dev_vdbg(dev, "Creating usbdrd_phy phy\n");
|
||||
|
||||
for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) {
|
||||
struct phy *phy = devm_phy_create(dev, &exynos5_usbdrd_phy_ops,
|
||||
NULL);
|
||||
if (IS_ERR(phy)) {
|
||||
dev_err(dev, "Failed to create usbdrd_phy phy\n");
|
||||
return PTR_ERR(phy);
|
||||
}
|
||||
|
||||
phy_drd->phys[i].phy = phy;
|
||||
phy_drd->phys[i].index = i;
|
||||
phy_drd->phys[i].reg_pmu = reg_pmu;
|
||||
phy_drd->phys[i].pmu_offset = pmu_offset;
|
||||
phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i];
|
||||
phy_set_drvdata(phy, &phy_drd->phys[i]);
|
||||
}
|
||||
|
||||
phy_provider = devm_of_phy_provider_register(dev,
|
||||
exynos5_usbdrd_phy_xlate);
|
||||
if (IS_ERR(phy_provider)) {
|
||||
dev_err(phy_drd->dev, "Failed to register phy provider\n");
|
||||
return PTR_ERR(phy_provider);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver exynos5_usb3drd_phy = {
|
||||
.probe = exynos5_usbdrd_phy_probe,
|
||||
.driver = {
|
||||
.of_match_table = exynos5_usbdrd_phy_of_match,
|
||||
.name = "exynos5_usb3drd_phy",
|
||||
.owner = THIS_MODULE,
|
||||
}
|
||||
};
|
||||
|
||||
module_platform_driver(exynos5_usb3drd_phy);
|
||||
MODULE_DESCRIPTION("Samsung EXYNOS5 SoCs USB 3.0 DRD controller PHY driver");
|
||||
MODULE_AUTHOR("Vivek Gautam <gautam.vivek@samsung.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:exynos5_usb3drd_phy");
|
||||
|
|
@ -246,6 +246,6 @@ static struct platform_driver exynos_sata_phy_driver = {
|
|||
module_platform_driver(exynos_sata_phy_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Samsung SerDes PHY driver");
|
||||
MODULE_LICENSE("GPL V2");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Girish K S <ks.giri@samsung.com>");
|
||||
MODULE_AUTHOR("Yuvaraj C D <yuvaraj.cd@samsung.com>");
|
||||
|
|
|
|||
|
|
@ -275,18 +275,34 @@ static int omap_usb2_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(phy_provider))
|
||||
return PTR_ERR(phy_provider);
|
||||
|
||||
phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
|
||||
phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
|
||||
if (IS_ERR(phy->wkupclk)) {
|
||||
dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
|
||||
return PTR_ERR(phy->wkupclk);
|
||||
dev_warn(&pdev->dev, "unable to get wkupclk, trying old name\n");
|
||||
phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
|
||||
if (IS_ERR(phy->wkupclk)) {
|
||||
dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
|
||||
return PTR_ERR(phy->wkupclk);
|
||||
} else {
|
||||
dev_warn(&pdev->dev,
|
||||
"found usb_phy_cm_clk32k, please fix DTS\n");
|
||||
}
|
||||
}
|
||||
clk_prepare(phy->wkupclk);
|
||||
|
||||
phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
|
||||
if (IS_ERR(phy->optclk))
|
||||
dev_vdbg(&pdev->dev, "unable to get refclk960m\n");
|
||||
else
|
||||
phy->optclk = devm_clk_get(phy->dev, "refclk");
|
||||
if (IS_ERR(phy->optclk)) {
|
||||
dev_dbg(&pdev->dev, "unable to get refclk, trying old name\n");
|
||||
phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
|
||||
if (IS_ERR(phy->optclk)) {
|
||||
dev_dbg(&pdev->dev,
|
||||
"unable to get usb_otg_ss_refclk960m\n");
|
||||
} else {
|
||||
dev_warn(&pdev->dev,
|
||||
"found usb_otg_ss_refclk960m, please fix DTS\n");
|
||||
}
|
||||
} else {
|
||||
clk_prepare(phy->optclk);
|
||||
}
|
||||
|
||||
usb_add_phy_dev(&phy->phy);
|
||||
|
||||
|
|
|
|||
|
|
@ -61,7 +61,6 @@
|
|||
#define MAX_PHYS 3
|
||||
|
||||
struct sun4i_usb_phy_data {
|
||||
struct clk *clk;
|
||||
void __iomem *base;
|
||||
struct mutex mutex;
|
||||
int num_phys;
|
||||
|
|
@ -71,6 +70,7 @@ struct sun4i_usb_phy_data {
|
|||
void __iomem *pmu;
|
||||
struct regulator *vbus;
|
||||
struct reset_control *reset;
|
||||
struct clk *clk;
|
||||
int index;
|
||||
} phys[MAX_PHYS];
|
||||
};
|
||||
|
|
@ -146,13 +146,13 @@ static int sun4i_usb_phy_init(struct phy *_phy)
|
|||
struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(data->clk);
|
||||
ret = clk_prepare_enable(phy->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = reset_control_deassert(phy->reset);
|
||||
if (ret) {
|
||||
clk_disable_unprepare(data->clk);
|
||||
clk_disable_unprepare(phy->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -170,11 +170,10 @@ static int sun4i_usb_phy_init(struct phy *_phy)
|
|||
static int sun4i_usb_phy_exit(struct phy *_phy)
|
||||
{
|
||||
struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
|
||||
struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
|
||||
|
||||
sun4i_usb_phy_passby(phy, 0);
|
||||
reset_control_assert(phy->reset);
|
||||
clk_disable_unprepare(data->clk);
|
||||
clk_disable_unprepare(phy->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -224,13 +223,9 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
|
|||
struct sun4i_usb_phy_data *data;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *pmu = NULL;
|
||||
struct phy_provider *phy_provider;
|
||||
struct reset_control *reset;
|
||||
struct regulator *vbus;
|
||||
bool dedicated_clocks;
|
||||
struct resource *res;
|
||||
struct phy *phy;
|
||||
char name[16];
|
||||
int i;
|
||||
|
||||
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
||||
|
|
@ -249,55 +244,64 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
|
|||
else
|
||||
data->disc_thresh = 2;
|
||||
|
||||
if (of_device_is_compatible(np, "allwinner,sun6i-a31-usb-phy"))
|
||||
dedicated_clocks = true;
|
||||
else
|
||||
dedicated_clocks = false;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
|
||||
data->base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(data->base))
|
||||
return PTR_ERR(data->base);
|
||||
|
||||
data->clk = devm_clk_get(dev, "usb_phy");
|
||||
if (IS_ERR(data->clk)) {
|
||||
dev_err(dev, "could not get usb_phy clock\n");
|
||||
return PTR_ERR(data->clk);
|
||||
}
|
||||
|
||||
/* Skip 0, 0 is the phy for otg which is not yet supported. */
|
||||
for (i = 1; i < data->num_phys; i++) {
|
||||
struct sun4i_usb_phy *phy = data->phys + i;
|
||||
char name[16];
|
||||
|
||||
snprintf(name, sizeof(name), "usb%d_vbus", i);
|
||||
vbus = devm_regulator_get_optional(dev, name);
|
||||
if (IS_ERR(vbus)) {
|
||||
if (PTR_ERR(vbus) == -EPROBE_DEFER)
|
||||
phy->vbus = devm_regulator_get_optional(dev, name);
|
||||
if (IS_ERR(phy->vbus)) {
|
||||
if (PTR_ERR(phy->vbus) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
vbus = NULL;
|
||||
phy->vbus = NULL;
|
||||
}
|
||||
|
||||
if (dedicated_clocks)
|
||||
snprintf(name, sizeof(name), "usb%d_phy", i);
|
||||
else
|
||||
strlcpy(name, "usb_phy", sizeof(name));
|
||||
|
||||
phy->clk = devm_clk_get(dev, name);
|
||||
if (IS_ERR(phy->clk)) {
|
||||
dev_err(dev, "failed to get clock %s\n", name);
|
||||
return PTR_ERR(phy->clk);
|
||||
}
|
||||
|
||||
snprintf(name, sizeof(name), "usb%d_reset", i);
|
||||
reset = devm_reset_control_get(dev, name);
|
||||
if (IS_ERR(reset)) {
|
||||
phy->reset = devm_reset_control_get(dev, name);
|
||||
if (IS_ERR(phy->reset)) {
|
||||
dev_err(dev, "failed to get reset %s\n", name);
|
||||
return PTR_ERR(reset);
|
||||
return PTR_ERR(phy->reset);
|
||||
}
|
||||
|
||||
if (i) { /* No pmu for usbc0 */
|
||||
snprintf(name, sizeof(name), "pmu%d", i);
|
||||
res = platform_get_resource_byname(pdev,
|
||||
IORESOURCE_MEM, name);
|
||||
pmu = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(pmu))
|
||||
return PTR_ERR(pmu);
|
||||
phy->pmu = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(phy->pmu))
|
||||
return PTR_ERR(phy->pmu);
|
||||
}
|
||||
|
||||
phy = devm_phy_create(dev, &sun4i_usb_phy_ops, NULL);
|
||||
if (IS_ERR(phy)) {
|
||||
phy->phy = devm_phy_create(dev, &sun4i_usb_phy_ops, NULL);
|
||||
if (IS_ERR(phy->phy)) {
|
||||
dev_err(dev, "failed to create PHY %d\n", i);
|
||||
return PTR_ERR(phy);
|
||||
return PTR_ERR(phy->phy);
|
||||
}
|
||||
|
||||
data->phys[i].phy = phy;
|
||||
data->phys[i].pmu = pmu;
|
||||
data->phys[i].vbus = vbus;
|
||||
data->phys[i].reset = reset;
|
||||
data->phys[i].index = i;
|
||||
phy_set_drvdata(phy, &data->phys[i]);
|
||||
phy->index = i;
|
||||
phy_set_drvdata(phy->phy, &data->phys[i]);
|
||||
}
|
||||
|
||||
dev_set_drvdata(dev, data);
|
||||
|
|
@ -311,6 +315,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
|
|||
static const struct of_device_id sun4i_usb_phy_of_match[] = {
|
||||
{ .compatible = "allwinner,sun4i-a10-usb-phy" },
|
||||
{ .compatible = "allwinner,sun5i-a13-usb-phy" },
|
||||
{ .compatible = "allwinner,sun6i-a31-usb-phy" },
|
||||
{ .compatible = "allwinner,sun7i-a20-usb-phy" },
|
||||
{ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Exynos5 SoC series Power Management Unit (PMU) register offsets
|
||||
* and bit definitions.
|
||||
*
|
||||
* Copyright (C) 2014 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_
|
||||
#define _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_
|
||||
|
||||
/* Exynos5 PMU register definitions */
|
||||
#define EXYNOS5_HDMI_PHY_CONTROL (0x700)
|
||||
#define EXYNOS5_USBDRD_PHY_CONTROL (0x704)
|
||||
|
||||
/* Exynos5250 specific register definitions */
|
||||
#define EXYNOS5_USBHOST_PHY_CONTROL (0x708)
|
||||
#define EXYNOS5_EFNAND_PHY_CONTROL (0x70c)
|
||||
#define EXYNOS5_MIPI_PHY0_CONTROL (0x710)
|
||||
#define EXYNOS5_MIPI_PHY1_CONTROL (0x714)
|
||||
#define EXYNOS5_ADC_PHY_CONTROL (0x718)
|
||||
#define EXYNOS5_MTCADC_PHY_CONTROL (0x71c)
|
||||
#define EXYNOS5_DPTX_PHY_CONTROL (0x720)
|
||||
#define EXYNOS5_SATA_PHY_CONTROL (0x724)
|
||||
|
||||
/* Exynos5420 specific register definitions */
|
||||
#define EXYNOS5420_USBDRD1_PHY_CONTROL (0x708)
|
||||
#define EXYNOS5420_USBHOST_PHY_CONTROL (0x70c)
|
||||
#define EXYNOS5420_MIPI_PHY0_CONTROL (0x714)
|
||||
#define EXYNOS5420_MIPI_PHY1_CONTROL (0x718)
|
||||
#define EXYNOS5420_MIPI_PHY2_CONTROL (0x71c)
|
||||
#define EXYNOS5420_ADC_PHY_CONTROL (0x720)
|
||||
#define EXYNOS5420_MTCADC_PHY_CONTROL (0x724)
|
||||
#define EXYNOS5420_DPTX_PHY_CONTROL (0x728)
|
||||
|
||||
#define EXYNOS5_PHY_ENABLE BIT(0)
|
||||
|
||||
#define EXYNOS5_MIPI_PHY_S_RESETN BIT(1)
|
||||
#define EXYNOS5_MIPI_PHY_M_RESETN BIT(2)
|
||||
|
||||
#endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */
|
||||
Loading…
Reference in New Issue