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drm/amdgpu: add hdp clock gating for Arcturus 

Add hdp CGLS for Arcturus in set common clockgating function

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Le Ma 2019-08-07 15:16:19 +08:00 committed by Alex Deucher
parent 6b76ce62bf
commit 6acb87acef
1 changed files with 6 additions and 1 deletions
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7
drivers/gpu/drm/amd/amdgpu/soc15.c
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@ -1259,7 +1259,8 @@ static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable
{
uint32_t def, data;
if (adev->asic_type == CHIP_VEGA20) {
if (adev->asic_type == CHIP_VEGA20 ||
adev->asic_type == CHIP_ARCTURUS) {
def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
@ -1391,6 +1392,10 @@ static int soc15_common_set_clockgating_state(void *handle,
soc15_update_rom_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
break;
case CHIP_ARCTURUS:
soc15_update_hdp_light_sleep(adev,
state == AMD_CG_STATE_GATE ? true : false);
break;
default:
break;
}