mirror of https://gitee.com/openkylin/linux.git
MIPS: Add probing & defs for VZ & guest features
Add a few new cpu-features.h definitions for VZ sub-features, namely the existence of the CP0_GuestCtl0Ext, CP0_GuestCtl1, and CP0_GuestCtl2 registers, and support for GuestID to dialias TLB entries belonging to different guests. Also add certain features present in the guest, with the naming scheme cpu_guest_has_*. These are added separately to the main options bitfield since they generally parallel similar features in the root context. A few of these (FPU, MSA, watchpoints, perf counters, CP0_[X]ContextConfig registers, MAAR registers, and probably others in future) can be dynamically configured in the guest context, for which the cpu_guest_has_dyn_* macros are added. [ralf@linux-mips.org: Resolve merge conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13231/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
James Hogan
Ralf Baechle
parent
7eb9111822
commit
6ad816e77e
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@ -120,6 +120,21 @@
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#ifndef kernel_uses_llsc
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#define kernel_uses_llsc cpu_has_llsc
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#endif
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#ifndef cpu_has_guestctl0ext
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#define cpu_has_guestctl0ext (cpu_data[0].options & MIPS_CPU_GUESTCTL0EXT)
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#endif
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#ifndef cpu_has_guestctl1
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#define cpu_has_guestctl1 (cpu_data[0].options & MIPS_CPU_GUESTCTL1)
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#endif
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#ifndef cpu_has_guestctl2
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#define cpu_has_guestctl2 (cpu_data[0].options & MIPS_CPU_GUESTCTL2)
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#endif
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#ifndef cpu_has_guestid
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#define cpu_has_guestid (cpu_data[0].options & MIPS_CPU_GUESTID)
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#endif
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#ifndef cpu_has_drg
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#define cpu_has_drg (cpu_data[0].options & MIPS_CPU_DRG)
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#endif
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#ifndef cpu_has_mips16
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#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
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#endif
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@ -458,4 +473,87 @@
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# define cpu_has_perf (cpu_data[0].options & MIPS_CPU_PERF)
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#endif
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/*
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* Guest capabilities
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*/
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#ifndef cpu_guest_has_conf1
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#define cpu_guest_has_conf1 (cpu_data[0].guest.conf & (1 << 1))
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#endif
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#ifndef cpu_guest_has_conf2
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#define cpu_guest_has_conf2 (cpu_data[0].guest.conf & (1 << 2))
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#endif
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#ifndef cpu_guest_has_conf3
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#define cpu_guest_has_conf3 (cpu_data[0].guest.conf & (1 << 3))
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#endif
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#ifndef cpu_guest_has_conf4
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#define cpu_guest_has_conf4 (cpu_data[0].guest.conf & (1 << 4))
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#endif
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#ifndef cpu_guest_has_conf5
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#define cpu_guest_has_conf5 (cpu_data[0].guest.conf & (1 << 5))
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#endif
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#ifndef cpu_guest_has_conf6
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#define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6))
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#endif
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#ifndef cpu_guest_has_conf7
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#define cpu_guest_has_conf7 (cpu_data[0].guest.conf & (1 << 7))
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#endif
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#ifndef cpu_guest_has_fpu
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#define cpu_guest_has_fpu (cpu_data[0].guest.options & MIPS_CPU_FPU)
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#endif
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#ifndef cpu_guest_has_watch
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#define cpu_guest_has_watch (cpu_data[0].guest.options & MIPS_CPU_WATCH)
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#endif
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#ifndef cpu_guest_has_contextconfig
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#define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC)
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#endif
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#ifndef cpu_guest_has_segments
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#define cpu_guest_has_segments (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS)
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#endif
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#ifndef cpu_guest_has_badinstr
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#define cpu_guest_has_badinstr (cpu_data[0].guest.options & MIPS_CPU_BADINSTR)
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#endif
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#ifndef cpu_guest_has_badinstrp
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#define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP)
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#endif
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#ifndef cpu_guest_has_htw
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#define cpu_guest_has_htw (cpu_data[0].guest.options & MIPS_CPU_HTW)
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#endif
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#ifndef cpu_guest_has_msa
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#define cpu_guest_has_msa (cpu_data[0].guest.ases & MIPS_ASE_MSA)
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#endif
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#ifndef cpu_guest_has_kscr
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#define cpu_guest_has_kscr(n) (cpu_data[0].guest.kscratch_mask & (1u << (n)))
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#endif
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#ifndef cpu_guest_has_rw_llb
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#define cpu_guest_has_rw_llb (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB))
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#endif
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#ifndef cpu_guest_has_perf
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#define cpu_guest_has_perf (cpu_data[0].guest.options & MIPS_CPU_PERF)
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#endif
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#ifndef cpu_guest_has_maar
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#define cpu_guest_has_maar (cpu_data[0].guest.options & MIPS_CPU_MAAR)
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#endif
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/*
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* Guest dynamic capabilities
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*/
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#ifndef cpu_guest_has_dyn_fpu
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#define cpu_guest_has_dyn_fpu (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU)
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#endif
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#ifndef cpu_guest_has_dyn_watch
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#define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH)
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#endif
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#ifndef cpu_guest_has_dyn_contextconfig
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#define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC)
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#endif
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#ifndef cpu_guest_has_dyn_perf
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#define cpu_guest_has_dyn_perf (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF)
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#endif
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#ifndef cpu_guest_has_dyn_msa
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#define cpu_guest_has_dyn_msa (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA)
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#endif
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#ifndef cpu_guest_has_dyn_maar
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#define cpu_guest_has_dyn_maar (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR)
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#endif
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#endif /* __ASM_CPU_FEATURES_H */
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@ -28,6 +28,15 @@ struct cache_desc {
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unsigned char flags; /* Flags describing cache properties */
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};
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struct guest_info {
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unsigned long ases;
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unsigned long ases_dyn;
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unsigned long long options;
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unsigned long long options_dyn;
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u8 conf;
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u8 kscratch_mask;
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};
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/*
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* Flag definitions
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*/
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@ -95,6 +104,11 @@ struct cpuinfo_mips {
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* htw_start/htw_stop calls
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*/
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unsigned int htw_seq;
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/* VZ & Guest features */
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struct guest_info guest;
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unsigned int gtoffset_mask;
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unsigned int guestid_mask;
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} __attribute__((aligned(SMP_CACHE_BYTES)));
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extern struct cpuinfo_mips cpu_data[];
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@ -409,6 +409,11 @@ enum cpu_type_enum {
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#define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */
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#define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */
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#define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */
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#define MIPS_CPU_GUESTCTL0EXT MBIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
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#define MIPS_CPU_GUESTCTL1 MBIT_ULL(49) /* CPU has VZ GuestCtl1 register */
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#define MIPS_CPU_GUESTCTL2 MBIT_ULL(50) /* CPU has VZ GuestCtl2 register */
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#define MIPS_CPU_GUESTID MBIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
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#define MIPS_CPU_DRG MBIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
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/*
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* CPU ASE encodings
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@ -915,6 +915,235 @@ static void decode_configs(struct cpuinfo_mips *c)
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#endif
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}
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/*
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* Probe for certain guest capabilities by writing config bits and reading back.
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* Finally write back the original value.
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*/
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#define probe_gc0_config(name, maxconf, bits) \
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do { \
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unsigned int tmp; \
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tmp = read_gc0_##name(); \
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write_gc0_##name(tmp | (bits)); \
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back_to_back_c0_hazard(); \
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maxconf = read_gc0_##name(); \
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write_gc0_##name(tmp); \
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} while (0)
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/*
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* Probe for dynamic guest capabilities by changing certain config bits and
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* reading back to see if they change. Finally write back the original value.
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*/
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#define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
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do { \
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maxconf = read_gc0_##name(); \
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write_gc0_##name(maxconf ^ (bits)); \
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back_to_back_c0_hazard(); \
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dynconf = maxconf ^ read_gc0_##name(); \
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write_gc0_##name(maxconf); \
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maxconf |= dynconf; \
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} while (0)
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static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
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{
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unsigned int config0;
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probe_gc0_config(config, config0, MIPS_CONF_M);
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if (config0 & MIPS_CONF_M)
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c->guest.conf |= BIT(1);
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return config0 & MIPS_CONF_M;
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}
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static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
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{
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unsigned int config1, config1_dyn;
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probe_gc0_config_dyn(config1, config1, config1_dyn,
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MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
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MIPS_CONF1_FP);
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if (config1 & MIPS_CONF1_FP)
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c->guest.options |= MIPS_CPU_FPU;
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if (config1_dyn & MIPS_CONF1_FP)
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c->guest.options_dyn |= MIPS_CPU_FPU;
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if (config1 & MIPS_CONF1_WR)
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c->guest.options |= MIPS_CPU_WATCH;
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if (config1_dyn & MIPS_CONF1_WR)
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c->guest.options_dyn |= MIPS_CPU_WATCH;
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if (config1 & MIPS_CONF1_PC)
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c->guest.options |= MIPS_CPU_PERF;
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if (config1_dyn & MIPS_CONF1_PC)
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c->guest.options_dyn |= MIPS_CPU_PERF;
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if (config1 & MIPS_CONF_M)
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c->guest.conf |= BIT(2);
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return config1 & MIPS_CONF_M;
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}
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static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
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{
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unsigned int config2;
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probe_gc0_config(config2, config2, MIPS_CONF_M);
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if (config2 & MIPS_CONF_M)
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c->guest.conf |= BIT(3);
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return config2 & MIPS_CONF_M;
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}
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static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
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{
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unsigned int config3, config3_dyn;
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probe_gc0_config_dyn(config3, config3, config3_dyn,
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MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_CTXTC);
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if (config3 & MIPS_CONF3_CTXTC)
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c->guest.options |= MIPS_CPU_CTXTC;
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if (config3_dyn & MIPS_CONF3_CTXTC)
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c->guest.options_dyn |= MIPS_CPU_CTXTC;
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if (config3 & MIPS_CONF3_PW)
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c->guest.options |= MIPS_CPU_HTW;
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if (config3 & MIPS_CONF3_SC)
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c->guest.options |= MIPS_CPU_SEGMENTS;
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if (config3 & MIPS_CONF3_BI)
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c->guest.options |= MIPS_CPU_BADINSTR;
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if (config3 & MIPS_CONF3_BP)
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c->guest.options |= MIPS_CPU_BADINSTRP;
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if (config3 & MIPS_CONF3_MSA)
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c->guest.ases |= MIPS_ASE_MSA;
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if (config3_dyn & MIPS_CONF3_MSA)
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c->guest.ases_dyn |= MIPS_ASE_MSA;
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if (config3 & MIPS_CONF_M)
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c->guest.conf |= BIT(4);
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return config3 & MIPS_CONF_M;
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}
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static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
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{
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unsigned int config4;
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probe_gc0_config(config4, config4,
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MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
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c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
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>> MIPS_CONF4_KSCREXIST_SHIFT;
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if (config4 & MIPS_CONF_M)
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c->guest.conf |= BIT(5);
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return config4 & MIPS_CONF_M;
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}
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static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
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{
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unsigned int config5, config5_dyn;
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probe_gc0_config_dyn(config5, config5, config5_dyn,
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MIPS_CONF_M | MIPS_CONF5_MRP);
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if (config5 & MIPS_CONF5_MRP)
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c->guest.options |= MIPS_CPU_MAAR;
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if (config5_dyn & MIPS_CONF5_MRP)
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c->guest.options_dyn |= MIPS_CPU_MAAR;
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if (config5 & MIPS_CONF5_LLB)
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c->guest.options |= MIPS_CPU_RW_LLB;
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if (config5 & MIPS_CONF_M)
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c->guest.conf |= BIT(6);
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return config5 & MIPS_CONF_M;
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}
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static inline void decode_guest_configs(struct cpuinfo_mips *c)
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{
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unsigned int ok;
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ok = decode_guest_config0(c);
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if (ok)
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ok = decode_guest_config1(c);
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if (ok)
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ok = decode_guest_config2(c);
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if (ok)
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ok = decode_guest_config3(c);
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if (ok)
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ok = decode_guest_config4(c);
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if (ok)
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decode_guest_config5(c);
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}
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static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
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{
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unsigned int guestctl0, temp;
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guestctl0 = read_c0_guestctl0();
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if (guestctl0 & MIPS_GCTL0_G0E)
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c->options |= MIPS_CPU_GUESTCTL0EXT;
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if (guestctl0 & MIPS_GCTL0_G1)
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c->options |= MIPS_CPU_GUESTCTL1;
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if (guestctl0 & MIPS_GCTL0_G2)
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c->options |= MIPS_CPU_GUESTCTL2;
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if (!(guestctl0 & MIPS_GCTL0_RAD)) {
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c->options |= MIPS_CPU_GUESTID;
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/*
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* Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
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* first, otherwise all data accesses will be fully virtualised
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* as if they were performed by guest mode.
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*/
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write_c0_guestctl1(0);
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tlbw_use_hazard();
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write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
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back_to_back_c0_hazard();
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temp = read_c0_guestctl0();
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if (temp & MIPS_GCTL0_DRG) {
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write_c0_guestctl0(guestctl0);
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c->options |= MIPS_CPU_DRG;
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}
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}
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}
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static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
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{
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if (cpu_has_guestid) {
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/* determine the number of bits of GuestID available */
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write_c0_guestctl1(MIPS_GCTL1_ID);
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back_to_back_c0_hazard();
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c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
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>> MIPS_GCTL1_ID_SHIFT;
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write_c0_guestctl1(0);
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}
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}
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static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
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{
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/* determine the number of bits of GTOffset available */
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write_c0_gtoffset(0xffffffff);
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back_to_back_c0_hazard();
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c->gtoffset_mask = read_c0_gtoffset();
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write_c0_gtoffset(0);
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}
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static inline void cpu_probe_vz(struct cpuinfo_mips *c)
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{
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cpu_probe_guestctl0(c);
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if (cpu_has_guestctl1)
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cpu_probe_guestctl1(c);
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cpu_probe_gtoffset(c);
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decode_guest_configs(c);
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}
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#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
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| MIPS_CPU_COUNTER)
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@ -1817,6 +2046,9 @@ void cpu_probe(void)
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elf_hwcap |= HWCAP_MIPS_MSA;
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}
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if (cpu_has_vz)
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cpu_probe_vz(c);
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cpu_probe_vmbits(c);
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#ifdef CONFIG_64BIT
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