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ARMv7: Do not set TTBR0 in __v7_setup 

This register is set in __enable_mmu in the head.S file.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Catalin Marinas 2008-11-06 13:23:08 +00:00
parent 376e14218d
commit 6b07d7fea0
1 changed files with 0 additions and 1 deletions
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arch/arm/mm/proc-v7.S
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@ -175,7 +175,6 @@ __v7_setup:
mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
mcr p15, 0, r10, c2, c0, 2 @ TTB control register mcr p15, 0, r10, c2, c0, 2 @ TTB control register
orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
mcr p15, 0, r4, c2, c0, 0 @ load TTB0
mcr p15, 0, r4, c2, c0, 1 @ load TTB1 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
mov r10, #0x1f @ domains 0, 1 = manager mov r10, #0x1f @ domains 0, 1 = manager
mcr p15, 0, r10, c3, c0, 0 @ load domain access register mcr p15, 0, r10, c3, c0, 0 @ load domain access register