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serial: 8250_exar: No need to autoconfigure Exar ports 

Since we have a separate driver there is no need to autoconfigure ports,
we already know what they are.

Drop autoconfiguration in 8250_port and move type detection to 8250_exar.

Cc: Aaron Sierra <asierra@xes-inc.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20190731170558.52897-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Andy Shevchenko 2019-07-31 20:05:56 +03:00 committed by Greg Kroah-Hartman
parent 6aa57f1618
commit 6be254c211
2 changed files with 17 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/tty/serial/8250/8250_exar.c
View File

@ -36,6 +36,7 @@
#define UART_EXAR_INT0 0x80
#define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
#define UART_EXAR_DVID 0x8d /* Device identification */
#define UART_EXAR_FCTR 0x08 /* Feature Control Register */
#define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
@ -133,12 +134,27 @@ static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
{
const struct exar8250_board *board = priv->board;
unsigned int bar = 0;
unsigned char status;
port->port.iotype = UPIO_MEM;
port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
port->port.membase = priv->virt + offset;
port->port.regshift = board->reg_shift;
/*
* XR17V35x UARTs have an extra divisor register, DLD that gets enabled
* with when DLAB is set which will cause the device to incorrectly match
* and assign port type to PORT_16650. The EFR for this UART is found
* at offset 0x09. Instead check the Deice ID (DVID) register
* for a 2, 4 or 8 port UART.
*/
status = readb(port->port.membase + UART_EXAR_DVID);
if (status == 0x82 || status == 0x84 || status == 0x88) {
port->port.type = PORT_XR17V35X;
} else {
port->port.type = PORT_XR17D15X;
}
return 0;
}
@ -494,8 +510,7 @@ exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
return rc;
memset(&uart, 0, sizeof(uart));
uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ
| UPF_EXAR_EFR;
uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
uart.port.irq = pci_irq_vector(pcidev, 0);
uart.port.dev = &pcidev->dev;

34
drivers/tty/serial/8250/8250_port.c
View File

@ -45,7 +45,6 @@
*/
#define UART_EXAR_INT0 0x80
#define UART_EXAR_SLEEP 0x8b /* Sleep mode */
#define UART_EXAR_DVID 0x8d /* Device identification */
/* Nuvoton NPCM timeout register */
#define UART_NPCM_TOR 7
@ -1011,27 +1010,6 @@ static void autoconfig_16550a(struct uart_8250_port *up)
up->port.type = PORT_16550A;
up->capabilities |= UART_CAP_FIFO;
/*
* XR17V35x UARTs have an extra divisor register, DLD
* that gets enabled with when DLAB is set which will
* cause the device to incorrectly match and assign
* port type to PORT_16650. The EFR for this UART is
* found at offset 0x09. Instead check the Deice ID (DVID)
* register for a 2, 4 or 8 port UART.
*/
if (up->port.flags & UPF_EXAR_EFR) {
status1 = serial_in(up, UART_EXAR_DVID);
if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
DEBUG_AUTOCONF("Exar XR17V35x ");
up->port.type = PORT_XR17V35X;
up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
UART_CAP_SLEEP;
return;
}
}
/*
* Check for presence of the EFR when DLAB is set.
* Only ST16C650V1 UARTs pass this test.
@ -1170,18 +1148,6 @@ static void autoconfig_16550a(struct uart_8250_port *up)
}
serial_out(up, UART_IER, iersave);
/*
* Exar uarts have EFR in a weird location
*/
if (up->port.flags & UPF_EXAR_EFR) {
DEBUG_AUTOCONF("Exar XR17D15x ");
up->port.type = PORT_XR17D15X;
up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
UART_CAP_SLEEP;
return;
}
/*
* We distinguish between 16550A and U6 16550A by counting
* how many bytes are in the FIFO.