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[SPARC64]: Move index info pci_pbm_info. 

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2007-05-07 23:49:01 -07:00
parent e9870c4c0a
commit 6c108f1299
9 changed files with 137 additions and 159 deletions
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10
arch/sparc64/kernel/pci.c
View File

@ -50,8 +50,8 @@ asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
/* List of all PCI controllers found in the system. */
struct pci_pbm_info *pci_pbm_root = NULL;
/* Each PCI controller found gets a unique index. */
int pci_num_controllers = 0;
/* Each PBM found gets a unique index. */
int pci_num_pbms = 0;
volatile int pci_poke_in_progress;
volatile int pci_poke_cpu = -1;
@ -1077,11 +1077,7 @@ int pci_domain_nr(struct pci_bus *pbus)
if (pbm == NULL || pbm->parent == NULL) {
ret = -ENXIO;
} else {
struct pci_controller_info *p = pbm->parent;
ret = p->index;
ret = ((ret << 1) +
((pbm == &pbm->parent->pbm_B) ? 1 : 0));
ret = pbm->index;
}
return ret;

30
arch/sparc64/kernel/pci_common.c
View File

@ -163,8 +163,7 @@ void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
}
/* Generic helper routines for PCI error reporting. */
void pci_scan_for_target_abort(struct pci_controller_info *p,
struct pci_pbm_info *pbm,
void pci_scan_for_target_abort(struct pci_pbm_info *pbm,
struct pci_bus *pbus)
{
struct pci_dev *pdev;
@ -179,18 +178,16 @@ void pci_scan_for_target_abort(struct pci_controller_info *p,
PCI_STATUS_REC_TARGET_ABORT));
if (error_bits) {
pci_write_config_word(pdev, PCI_STATUS, error_bits);
printk("PCI%d(PBM%c): Device [%s] saw Target Abort [%016x]\n",
p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
pci_name(pdev), status);
printk("%s: Device %s saw Target Abort [%016x]\n",
pbm->name, pci_name(pdev), status);
}
}
list_for_each_entry(bus, &pbus->children, node)
pci_scan_for_target_abort(p, pbm, bus);
pci_scan_for_target_abort(pbm, bus);
}
void pci_scan_for_master_abort(struct pci_controller_info *p,
struct pci_pbm_info *pbm,
void pci_scan_for_master_abort(struct pci_pbm_info *pbm,
struct pci_bus *pbus)
{
struct pci_dev *pdev;
@ -204,18 +201,16 @@ void pci_scan_for_master_abort(struct pci_controller_info *p,
(status & (PCI_STATUS_REC_MASTER_ABORT));
if (error_bits) {
pci_write_config_word(pdev, PCI_STATUS, error_bits);
printk("PCI%d(PBM%c): Device [%s] received Master Abort [%016x]\n",
p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
pci_name(pdev), status);
printk("%s: Device %s received Master Abort [%016x]\n",
pbm->name, pci_name(pdev), status);
}
}
list_for_each_entry(bus, &pbus->children, node)
pci_scan_for_master_abort(p, pbm, bus);
pci_scan_for_master_abort(pbm, bus);
}
void pci_scan_for_parity_error(struct pci_controller_info *p,
struct pci_pbm_info *pbm,
void pci_scan_for_parity_error(struct pci_pbm_info *pbm,
struct pci_bus *pbus)
{
struct pci_dev *pdev;
@ -230,12 +225,11 @@ void pci_scan_for_parity_error(struct pci_controller_info *p,
PCI_STATUS_DETECTED_PARITY));
if (error_bits) {
pci_write_config_word(pdev, PCI_STATUS, error_bits);
printk("PCI%d(PBM%c): Device [%s] saw Parity Error [%016x]\n",
p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
pci_name(pdev), status);
printk("%s: Device %s saw Parity Error [%016x]\n",
pbm->name, pci_name(pdev), status);
}
}
list_for_each_entry(bus, &pbus->children, node)
pci_scan_for_parity_error(p, pbm, bus);
pci_scan_for_parity_error(pbm, bus);
}

4
arch/sparc64/kernel/pci_fire.c
View File

@ -317,6 +317,8 @@ static void pci_fire_pbm_init(struct pci_controller_info *p,
pbm->scan_bus = pci_fire_scan_bus;
pbm->pci_ops = &pci_fire_ops;
pbm->index = pci_num_pbms++;
pbm->portid = portid;
pbm->parent = p;
pbm->prom_node = dp;
@ -373,8 +375,6 @@ void fire_pci_init(struct device_node *dp, const char *model_name)
p->pbm_B.iommu = iommu;
p->index = pci_num_controllers++;
/* XXX MSI support XXX */
/* Like PSYCHO and SCHIZO we have a 2GB aligned area

8
arch/sparc64/kernel/pci_impl.h
View File

@ -14,7 +14,7 @@
extern struct pci_pbm_info *pci_pbm_root;
extern unsigned long pci_memspace_mask;
extern int pci_num_controllers;
extern int pci_num_pbms;
/* PCI bus scanning and fixup support. */
extern void pci_get_pbm_props(struct pci_pbm_info *pbm);
@ -31,9 +31,9 @@ extern int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
u32 value);
/* Error reporting support. */
extern void pci_scan_for_target_abort(struct pci_controller_info *, struct pci_pbm_info *, struct pci_bus *);
extern void pci_scan_for_master_abort(struct pci_controller_info *, struct pci_pbm_info *, struct pci_bus *);
extern void pci_scan_for_parity_error(struct pci_controller_info *, struct pci_pbm_info *, struct pci_bus *);
extern void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *);
extern void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *);
extern void pci_scan_for_parity_error(struct pci_pbm_info *, struct pci_bus *);
/* Configuration space access. */
extern void pci_config_read8(u8 *addr, u8 *ret);

77
arch/sparc64/kernel/pci_psycho.c
View File

@ -268,7 +268,6 @@ static unsigned long stc_line_buf[16];
static void __psycho_check_one_stc(struct pci_pbm_info *pbm,
int is_pbm_a)
{
struct pci_controller_info *p = pbm->parent;
struct strbuf *strbuf = &pbm->stc;
unsigned long regbase = pbm->controller_regs;
unsigned long err_base, tag_base, line_base;
@ -326,9 +325,8 @@ static void __psycho_check_one_stc(struct pci_pbm_info *pbm,
unsigned long errval = stc_error_buf[j];
if (errval != 0) {
saw_error++;
printk("PSYCHO%d(PBM%c): STC_ERR(%d)[wr(%d)rd(%d)]\n",
p->index,
(is_pbm_a ? 'A' : 'B'),
printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
pbm->name,
j,
(errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
(errval & PSYCHO_STCERR_READ) ? 1 : 0);
@ -337,18 +335,16 @@ static void __psycho_check_one_stc(struct pci_pbm_info *pbm,
if (saw_error != 0) {
unsigned long tagval = stc_tag_buf[i];
unsigned long lineval = stc_line_buf[i];
printk("PSYCHO%d(PBM%c): STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
p->index,
(is_pbm_a ? 'A' : 'B'),
printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
pbm->name,
i,
((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
(tagval & PSYCHO_STCTAG_VPN),
((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
printk("PSYCHO%d(PBM%c): STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
"V(%d)FOFN(%d)]\n",
p->index,
(is_pbm_a ? 'A' : 'B'),
pbm->name,
i,
((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
@ -411,7 +407,6 @@ static void psycho_check_iommu_error(struct pci_pbm_info *pbm,
unsigned long afar,
enum psycho_error_type type)
{
struct pci_controller_info *p = pbm->parent;
struct iommu *iommu = pbm->iommu;
unsigned long iommu_tag[16];
unsigned long iommu_data[16];
@ -443,8 +438,8 @@ static void psycho_check_iommu_error(struct pci_pbm_info *pbm,
type_string = "ECC Error";
break;
};
printk("PSYCHO%d: IOMMU Error, type[%s]\n",
p->index, type_string);
printk("%s: IOMMU Error, type[%s]\n",
pbm->name, type_string);
/* Put the IOMMU into diagnostic mode and probe
* it's TLB for entries with error status.
@ -497,14 +492,14 @@ static void psycho_check_iommu_error(struct pci_pbm_info *pbm,
type_string = "ECC Error";
break;
};
printk("PSYCHO%d: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
p->index, i, type_string,
printk("%s: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
pbm->name, i, type_string,
((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
(tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
printk("PSYCHO%d: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
p->index, i,
printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
pbm->name, i,
((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
(data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
@ -555,22 +550,22 @@ static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
psycho_write(afsr_reg, error_bits);
/* Log the error. */
printk("PSYCHO%d: Uncorrectable Error, primary error type[%s]\n",
p->index,
printk("%s: Uncorrectable Error, primary error type[%s]\n",
pbm->name,
(((error_bits & PSYCHO_UEAFSR_PPIO) ?
"PIO" :
((error_bits & PSYCHO_UEAFSR_PDRD) ?
"DMA Read" :
((error_bits & PSYCHO_UEAFSR_PDWR) ?
"DMA Write" : "???")))));
printk("PSYCHO%d: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
p->index,
printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
pbm->name,
(afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
(afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
(afsr & PSYCHO_UEAFSR_MID) >> 24UL,
((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
printk("PSYCHO%d: UE AFAR [%016lx]\n", p->index, afar);
printk("PSYCHO%d: UE Secondary errors [", p->index);
printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
printk("%s: UE Secondary errors [", pbm->name);
reported = 0;
if (afsr & PSYCHO_UEAFSR_SPIO) {
reported++;
@ -615,7 +610,6 @@ static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
{
struct pci_pbm_info *pbm = dev_id;
struct pci_controller_info *p = pbm->parent;
unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR;
unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR;
unsigned long afsr, afar, error_bits;
@ -634,8 +628,8 @@ static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
psycho_write(afsr_reg, error_bits);
/* Log the error. */
printk("PSYCHO%d: Correctable Error, primary error type[%s]\n",
p->index,
printk("%s: Correctable Error, primary error type[%s]\n",
pbm->name,
(((error_bits & PSYCHO_CEAFSR_PPIO) ?
"PIO" :
((error_bits & PSYCHO_CEAFSR_PDRD) ?
@ -646,16 +640,16 @@ static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
/* XXX Use syndrome and afar to print out module string just like
* XXX UDB CE trap handler does... -DaveM
*/
printk("PSYCHO%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
"UPA_MID[%02lx] was_block(%d)\n",
p->index,
pbm->name,
(afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
(afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
(afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
(afsr & PSYCHO_CEAFSR_MID) >> 24UL,
((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
printk("PSYCHO%d: CE AFAR [%016lx]\n", p->index, afar);
printk("PSYCHO%d: CE Secondary errors [", p->index);
printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
printk("%s: CE Secondary errors [", pbm->name);
reported = 0;
if (afsr & PSYCHO_CEAFSR_SPIO) {
reported++;
@ -770,8 +764,8 @@ static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
psycho_write(afsr_reg, error_bits);
/* Log the error. */
printk("PSYCHO%d(PBM%c): PCI Error, primary error type[%s]\n",
p->index, (is_pbm_a ? 'A' : 'B'),
printk("%s: PCI Error, primary error type[%s]\n",
pbm->name,
(((error_bits & PSYCHO_PCIAFSR_PMA) ?
"Master Abort" :
((error_bits & PSYCHO_PCIAFSR_PTA) ?
@ -780,15 +774,13 @@ static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
"Excessive Retries" :
((error_bits & PSYCHO_PCIAFSR_PPERR) ?
"Parity Error" : "???"))))));
printk("PSYCHO%d(PBM%c): bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
p->index, (is_pbm_a ? 'A' : 'B'),
printk("%s: bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
pbm->name,
(afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
(afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
(afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
printk("PSYCHO%d(PBM%c): PCI AFAR [%016lx]\n",
p->index, (is_pbm_a ? 'A' : 'B'), afar);
printk("PSYCHO%d(PBM%c): PCI Secondary errors [",
p->index, (is_pbm_a ? 'A' : 'B'));
printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
printk("%s: PCI Secondary errors [", pbm->name);
reported = 0;
if (afsr & PSYCHO_PCIAFSR_SMA) {
reported++;
@ -821,10 +813,10 @@ static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
*/
if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
pci_scan_for_target_abort(pbm->parent, pbm, pbm->pci_bus);
pci_scan_for_target_abort(pbm, pbm->pci_bus);
}
if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
pci_scan_for_master_abort(pbm->parent, pbm, pbm->pci_bus);
pci_scan_for_master_abort(pbm, pbm->pci_bus);
/* For excessive retries, PSYCHO/PBM will abort the device
* and there is no way to specifically check for excessive
@ -834,7 +826,7 @@ static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
*/
if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
pci_scan_for_parity_error(pbm->parent, pbm, pbm->pci_bus);
pci_scan_for_parity_error(pbm, pbm->pci_bus);
return IRQ_HANDLED;
}
@ -1089,6 +1081,8 @@ static void psycho_pbm_init(struct pci_controller_info *p,
pbm->scan_bus = psycho_scan_bus;
pbm->pci_ops = &psycho_ops;
pbm->index = pci_num_pbms++;
pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
pbm->chip_version = 0;
prop = of_find_property(dp, "version#", NULL);
@ -1155,7 +1149,6 @@ void psycho_init(struct device_node *dp, char *model_name)
p->pbm_A.portid = upa_portid;
p->pbm_B.portid = upa_portid;
p->index = pci_num_controllers++;
prop = of_find_property(dp, "reg", NULL);
pr_regs = prop->value;

106
arch/sparc64/kernel/pci_sabre.c
View File

@ -494,11 +494,11 @@ static struct pci_ops sabre_ops = {
};
/* SABRE error handling support. */
static void sabre_check_iommu_error(struct pci_controller_info *p,
static void sabre_check_iommu_error(struct pci_pbm_info *pbm,
unsigned long afsr,
unsigned long afar)
{
struct iommu *iommu = p->pbm_A.iommu;
struct iommu *iommu = pbm->iommu;
unsigned long iommu_tag[16];
unsigned long iommu_data[16];
unsigned long flags;
@ -526,8 +526,8 @@ static void sabre_check_iommu_error(struct pci_controller_info *p,
type_string = "Unknown";
break;
};
printk("SABRE%d: IOMMU Error, type[%s]\n",
p->index, type_string);
printk("%s: IOMMU Error, type[%s]\n",
pbm->name, type_string);
/* Enter diagnostic mode and probe for error'd
* entries in the IOTLB.
@ -536,7 +536,7 @@ static void sabre_check_iommu_error(struct pci_controller_info *p,
sabre_write(iommu->iommu_control,
(control | SABRE_IOMMUCTRL_DENAB));
for (i = 0; i < 16; i++) {
unsigned long base = p->pbm_A.controller_regs;
unsigned long base = pbm->controller_regs;
iommu_tag[i] =
sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
@ -566,13 +566,13 @@ static void sabre_check_iommu_error(struct pci_controller_info *p,
type_string = "Unknown";
break;
};
printk("SABRE%d: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
p->index, i, tag, type_string,
printk("%s: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
pbm->name, i, tag, type_string,
((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
printk("SABRE%d: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
p->index, i, data,
printk("%s: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
pbm->name, i, data,
((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
@ -584,9 +584,9 @@ static void sabre_check_iommu_error(struct pci_controller_info *p,
static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
{
struct pci_controller_info *p = dev_id;
unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_UE_AFSR;
unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
struct pci_pbm_info *pbm = dev_id;
unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR;
unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
unsigned long afsr, afar, error_bits;
int reported;
@ -604,21 +604,21 @@ static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
sabre_write(afsr_reg, error_bits);
/* Log the error. */
printk("SABRE%d: Uncorrectable Error, primary error type[%s%s]\n",
p->index,
printk("%s: Uncorrectable Error, primary error type[%s%s]\n",
pbm->name,
((error_bits & SABRE_UEAFSR_PDRD) ?
"DMA Read" :
((error_bits & SABRE_UEAFSR_PDWR) ?
"DMA Write" : "???")),
((error_bits & SABRE_UEAFSR_PDTE) ?
":Translation Error" : ""));
printk("SABRE%d: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
p->index,
printk("%s: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
pbm->name,
(afsr & SABRE_UEAFSR_BMSK) >> 32UL,
(afsr & SABRE_UEAFSR_OFF) >> 29UL,
((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
printk("SABRE%d: UE AFAR [%016lx]\n", p->index, afar);
printk("SABRE%d: UE Secondary errors [", p->index);
printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
printk("%s: UE Secondary errors [", pbm->name);
reported = 0;
if (afsr & SABRE_UEAFSR_SDRD) {
reported++;
@ -637,16 +637,16 @@ static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
printk("]\n");
/* Interrogate IOMMU for error status. */
sabre_check_iommu_error(p, afsr, afar);
sabre_check_iommu_error(pbm, afsr, afar);
return IRQ_HANDLED;
}
static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
{
struct pci_controller_info *p = dev_id;
unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_CE_AFSR;
unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
struct pci_pbm_info *pbm = dev_id;
unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR;
unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
unsigned long afsr, afar, error_bits;
int reported;
@ -663,8 +663,8 @@ static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
sabre_write(afsr_reg, error_bits);
/* Log the error. */
printk("SABRE%d: Correctable Error, primary error type[%s]\n",
p->index,
printk("%s: Correctable Error, primary error type[%s]\n",
pbm->name,
((error_bits & SABRE_CEAFSR_PDRD) ?
"DMA Read" :
((error_bits & SABRE_CEAFSR_PDWR) ?
@ -673,15 +673,15 @@ static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
/* XXX Use syndrome and afar to print out module string just like
* XXX UDB CE trap handler does... -DaveM
*/
printk("SABRE%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
"was_block(%d)\n",
p->index,
pbm->name,
(afsr & SABRE_CEAFSR_ESYND) >> 48UL,
(afsr & SABRE_CEAFSR_BMSK) >> 32UL,
(afsr & SABRE_CEAFSR_OFF) >> 29UL,
((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
printk("SABRE%d: CE AFAR [%016lx]\n", p->index, afar);
printk("SABRE%d: CE Secondary errors [", p->index);
printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
printk("%s: CE Secondary errors [", pbm->name);
reported = 0;
if (afsr & SABRE_CEAFSR_SDRD) {
reported++;
@ -698,13 +698,13 @@ static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
return IRQ_HANDLED;
}
static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
static irqreturn_t sabre_pcierr_intr_other(struct pci_pbm_info *pbm)
{
unsigned long csr_reg, csr, csr_error_bits;
irqreturn_t ret = IRQ_NONE;
u16 stat;
csr_reg = p->pbm_A.controller_regs + SABRE_PCICTRL;
csr_reg = pbm->controller_regs + SABRE_PCICTRL;
csr = sabre_read(csr_reg);
csr_error_bits =
csr & SABRE_PCICTRL_SERR;
@ -714,8 +714,8 @@ static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
/* Log 'em. */
if (csr_error_bits & SABRE_PCICTRL_SERR)
printk("SABRE%d: PCI SERR signal asserted.\n",
p->index);
printk("%s: PCI SERR signal asserted.\n",
pbm->name);
ret = IRQ_HANDLED;
}
pci_bus_read_config_word(sabre_root_bus, 0,
@ -725,8 +725,8 @@ static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
PCI_STATUS_REC_TARGET_ABORT |
PCI_STATUS_REC_MASTER_ABORT |
PCI_STATUS_SIG_SYSTEM_ERROR)) {
printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n",
p->index, stat);
printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
pbm->name, stat);
pci_bus_write_config_word(sabre_root_bus, 0,
PCI_STATUS, 0xffff);
ret = IRQ_HANDLED;
@ -736,13 +736,13 @@ static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
{
struct pci_controller_info *p = dev_id;
struct pci_pbm_info *pbm = dev_id;
unsigned long afsr_reg, afar_reg;
unsigned long afsr, afar, error_bits;
int reported;
afsr_reg = p->pbm_A.controller_regs + SABRE_PIOAFSR;
afar_reg = p->pbm_A.controller_regs + SABRE_PIOAFAR;
afsr_reg = pbm->controller_regs + SABRE_PIOAFSR;
afar_reg = pbm->controller_regs + SABRE_PIOAFAR;
/* Latch error status. */
afar = sabre_read(afar_reg);
@ -755,12 +755,12 @@ static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
if (!error_bits)
return sabre_pcierr_intr_other(p);
return sabre_pcierr_intr_other(pbm);
sabre_write(afsr_reg, error_bits);
/* Log the error. */
printk("SABRE%d: PCI Error, primary error type[%s]\n",
p->index,
printk("%s: PCI Error, primary error type[%s]\n",
pbm->name,
(((error_bits & SABRE_PIOAFSR_PMA) ?
"Master Abort" :
((error_bits & SABRE_PIOAFSR_PTA) ?
@ -769,12 +769,12 @@ static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
"Excessive Retries" :
((error_bits & SABRE_PIOAFSR_PPERR) ?
"Parity Error" : "???"))))));
printk("SABRE%d: bytemask[%04lx] was_block(%d)\n",
p->index,
printk("%s: bytemask[%04lx] was_block(%d)\n",
pbm->name,
(afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
(afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
printk("SABRE%d: PCI AFAR [%016lx]\n", p->index, afar);
printk("SABRE%d: PCI Secondary errors [", p->index);
printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
printk("%s: PCI Secondary errors [", pbm->name);
reported = 0;
if (afsr & SABRE_PIOAFSR_SMA) {
reported++;
@ -806,11 +806,11 @@ static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
* a bug in the IOMMU support code or a PCI device driver.
*/
if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
sabre_check_iommu_error(p, afsr, afar);
pci_scan_for_target_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
sabre_check_iommu_error(pbm, afsr, afar);
pci_scan_for_target_abort(pbm, pbm->pci_bus);
}
if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA))
pci_scan_for_master_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
pci_scan_for_master_abort(pbm, pbm->pci_bus);
/* For excessive retries, SABRE/PBM will abort the device
* and there is no way to specifically check for excessive
@ -820,14 +820,13 @@ static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
*/
if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR))
pci_scan_for_parity_error(p, &p->pbm_A, p->pbm_A.pci_bus);
pci_scan_for_parity_error(pbm, pbm->pci_bus);
return IRQ_HANDLED;
}
static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
{
struct pci_controller_info *p = pbm->parent;
struct device_node *dp = pbm->prom_node;
struct of_device *op;
unsigned long base = pbm->controller_regs;
@ -858,15 +857,15 @@ static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));
request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", p);
request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
sabre_write(base + SABRE_CE_AFSR,
(SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));
request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", p);
request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
request_irq(op->irqs[0], sabre_pcierr_intr, 0,
"SABRE_PCIERR", p);
"SABRE_PCIERR", pbm);
tmp = sabre_read(base + SABRE_PCICTRL);
tmp |= SABRE_PCICTRL_ERREN;
@ -1006,6 +1005,8 @@ static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp
pbm->scan_bus = sabre_scan_bus;
pbm->pci_ops = &sabre_ops;
pbm->index = pci_num_pbms++;
pbm->chip_type = PBM_CHIP_TYPE_SABRE;
pbm->parent = p;
pbm->prom_node = dp;
@ -1062,7 +1063,6 @@ void sabre_init(struct device_node *dp, char *model_name)
pci_pbm_root = &p->pbm_A;
p->pbm_A.portid = upa_portid;
p->index = pci_num_controllers++;
/*
* Map in SABRE register set and report the presence of this SABRE.

51
arch/sparc64/kernel/pci_schizo.c
View File

@ -531,28 +531,28 @@ static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
schizo_write(afsr_reg, error_bits);
/* Log the error. */
printk("PCI%d: Uncorrectable Error, primary error type[%s]\n",
p->index,
printk("%s: Uncorrectable Error, primary error type[%s]\n",
pbm->name,
(((error_bits & SCHIZO_UEAFSR_PPIO) ?
"PIO" :
((error_bits & SCHIZO_UEAFSR_PDRD) ?
"DMA Read" :
((error_bits & SCHIZO_UEAFSR_PDWR) ?
"DMA Write" : "???")))));
printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
p->index,
printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
pbm->name,
(afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
(afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
(afsr & SCHIZO_UEAFSR_AID) >> 24UL);
printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
p->index,
printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
pbm->name,
(afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
(afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
(afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
(afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
(afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
printk("PCI%d: UE AFAR [%016lx]\n", p->index, afar);
printk("PCI%d: UE Secondary errors [", p->index);
printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
printk("%s: UE Secondary errors [", pbm->name);
reported = 0;
if (afsr & SCHIZO_UEAFSR_SPIO) {
reported++;
@ -593,7 +593,6 @@ static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
{
struct pci_pbm_info *pbm = dev_id;
struct pci_controller_info *p = pbm->parent;
unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR;
unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR;
unsigned long afsr, afar, error_bits;
@ -620,8 +619,8 @@ static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
schizo_write(afsr_reg, error_bits);
/* Log the error. */
printk("PCI%d: Correctable Error, primary error type[%s]\n",
p->index,
printk("%s: Correctable Error, primary error type[%s]\n",
pbm->name,
(((error_bits & SCHIZO_CEAFSR_PPIO) ?
"PIO" :
((error_bits & SCHIZO_CEAFSR_PDRD) ?
@ -632,20 +631,20 @@ static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
/* XXX Use syndrome and afar to print out module string just like
* XXX UDB CE trap handler does... -DaveM
*/
printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
p->index,
printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
pbm->name,
(afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
(afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
(afsr & SCHIZO_UEAFSR_AID) >> 24UL);
printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
p->index,
printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
pbm->name,
(afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
(afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
(afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
(afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
(afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
printk("PCI%d: CE AFAR [%016lx]\n", p->index, afar);
printk("PCI%d: CE Secondary errors [", p->index);
printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
printk("%s: CE Secondary errors [", pbm->name);
reported = 0;
if (afsr & SCHIZO_CEAFSR_SPIO) {
reported++;
@ -864,10 +863,10 @@ static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
*/
if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
schizo_check_iommu_error(p, PCI_ERR);
pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
pci_scan_for_target_abort(pbm, pbm->pci_bus);
}
if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
pci_scan_for_master_abort(pbm, pbm->pci_bus);
/* For excessive retries, PSYCHO/PBM will abort the device
* and there is no way to specifically check for excessive
@ -877,7 +876,7 @@ static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
*/
if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
pci_scan_for_parity_error(pbm, pbm->pci_bus);
return IRQ_HANDLED;
}
@ -932,14 +931,14 @@ static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
errlog & ~(SAFARI_ERRLOG_ERROUT));
if (!(errlog & BUS_ERROR_UNMAP)) {
printk("PCI%d: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
p->index, errlog);
printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
pbm->name, errlog);
return IRQ_HANDLED;
}
printk("PCI%d: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
p->index);
printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
pbm->name);
schizo_check_iommu_error(p, SAFARI_ERR);
return IRQ_HANDLED;
@ -1464,6 +1463,8 @@ static void schizo_pbm_init(struct pci_controller_info *p,
pbm->scan_bus = schizo_scan_bus;
pbm->pci_ops = &schizo_ops;
pbm->index = pci_num_pbms++;
pbm->portid = portid;
pbm->parent = p;
pbm->prom_node = dp;
@ -1536,8 +1537,6 @@ static void __schizo_init(struct device_node *dp, char *model_name, int chip_typ
p->pbm_B.iommu = iommu;
p->index = pci_num_controllers++;
/* Like PSYCHO we have a 2GB aligned area for memory space. */
pci_memspace_mask = 0x7fffffffUL;

4
arch/sparc64/kernel/pci_sun4v.c
View File

@ -1241,6 +1241,8 @@ static void pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node
pbm->scan_bus = pci_sun4v_scan_bus;
pbm->pci_ops = &pci_sun4v_ops;
pbm->index = pci_num_pbms++;
pbm->parent = p;
pbm->prom_node = dp;
@ -1304,8 +1306,6 @@ void sun4v_pci_init(struct device_node *dp, char *model_name)
p->pbm_B.iommu = iommu;
p->index = pci_num_controllers++;
/* Like PSYCHO and SCHIZO we have a 2GB aligned area
* for memory space.
*/

6
include/asm-sparc64/pbm.h
View File

@ -40,6 +40,7 @@ struct pci_controller_info;
struct pci_pbm_info {
struct pci_pbm_info *next;
int index;
/* PCI controller we sit under. */
struct pci_controller_info *parent;
@ -123,11 +124,6 @@ struct pci_pbm_info {
};
struct pci_controller_info {
/* Each controller gets a unique index, used mostly for
* error logging purposes.
*/
int index;
/* The PCI bus modules controlled by us. */
struct pci_pbm_info pbm_A;
struct pci_pbm_info pbm_B;