mirror of https://gitee.com/openkylin/linux.git
drm/i915/guc: Simplify intel_guc_init_hw()
Current version of intel_guc_init_hw() does a lot: - cares about submission - loads huc - implement WA This change offloads some of the logic to intel_uc_init_hw(), which now cares about the above. v2: rename guc_hw_reset and fix typo in define name (M. Wajdeczko) v3: rename once again v4: remove spurious comments and add some style (J. Lahtinen) v5: flow changes, got rid of dead checks (M. Wajdeczko) v6: rebase v7: rebase & onion teardown (J. Lahtinen) Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Michal Winiarski <michal.winiarski@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This commit is contained in:
Arkadiusz Hiler
Joonas Lahtinen
parent
d2be9f2f41
commit
6cd5a72c35
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@ -4541,7 +4541,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
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intel_mocs_init_l3cc_table(dev_priv);
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/* We can't enable contexts until all firmware is loaded */
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ret = intel_guc_init_hw(&dev_priv->guc);
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ret = intel_uc_init_hw(dev_priv);
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if (ret)
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goto out;
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@ -344,24 +344,6 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
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return ret;
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}
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static int guc_hw_reset(struct drm_i915_private *dev_priv)
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{
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int ret;
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u32 guc_status;
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ret = intel_guc_reset(dev_priv);
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if (ret) {
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DRM_ERROR("GuC reset failed, ret = %d\n", ret);
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return ret;
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}
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guc_status = I915_READ(GUC_STATUS);
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WARN(!(guc_status & GS_MIA_IN_RESET),
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"GuC status: 0x%x, MIA core expected to be in reset\n", guc_status);
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return ret;
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}
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/**
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* intel_guc_init_hw() - finish preparing the GuC for activity
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* @guc: intel_guc structure
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@ -379,41 +361,22 @@ int intel_guc_init_hw(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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const char *fw_path = guc->fw.path;
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int retries, ret, err;
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int ret;
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DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
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fw_path,
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intel_uc_fw_status_repr(guc->fw.fetch_status),
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intel_uc_fw_status_repr(guc->fw.load_status));
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/* Loading forbidden, or no firmware to load? */
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if (!i915.enable_guc_loading) {
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err = 0;
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goto fail;
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} else if (fw_path == NULL) {
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/* Device is known to have no uCode (e.g. no GuC) */
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err = -ENXIO;
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goto fail;
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if (!fw_path) {
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return -ENXIO;
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} else if (*fw_path == '\0') {
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/* Device has a GuC but we don't know what f/w to load? */
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WARN(1, "No GuC firmware known for this platform!\n");
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err = -ENODEV;
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goto fail;
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return -ENODEV;
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}
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/* Fetch failed, or already fetched but failed to load? */
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if (guc->fw.fetch_status != INTEL_UC_FIRMWARE_SUCCESS) {
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err = -EIO;
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goto fail;
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} else if (guc->fw.load_status == INTEL_UC_FIRMWARE_FAIL) {
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err = -ENOEXEC;
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goto fail;
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}
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gen9_reset_guc_interrupts(dev_priv);
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/* We need to notify the guc whenever we change the GGTT */
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i915_ggtt_enable_guc(dev_priv);
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if (guc->fw.fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
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return -EIO;
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guc->fw.load_status = INTEL_UC_FIRMWARE_PENDING;
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@ -421,102 +384,19 @@ int intel_guc_init_hw(struct intel_guc *guc)
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intel_uc_fw_status_repr(guc->fw.fetch_status),
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intel_uc_fw_status_repr(guc->fw.load_status));
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err = i915_guc_submission_init(dev_priv);
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if (err)
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goto fail;
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ret = guc_ucode_xfer(dev_priv);
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/*
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* WaEnableuKernelHeaderValidFix:skl,bxt
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* For BXT, this is only upto B0 but below WA is required for later
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* steppings also so this is extended as well.
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*/
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/* WaEnableGuCBootHashCheckNotSet:skl,bxt */
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for (retries = 3; ; ) {
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/*
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* Always reset the GuC just before (re)loading, so
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* that the state and timing are fairly predictable
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*/
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err = guc_hw_reset(dev_priv);
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if (err)
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goto fail;
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intel_huc_init_hw(&dev_priv->huc);
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err = guc_ucode_xfer(dev_priv);
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if (!err)
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break;
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if (--retries == 0)
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goto fail;
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DRM_INFO("GuC fw load failed: %d; will reset and "
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"retry %d more time(s)\n", err, retries);
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}
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if (ret)
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return -EAGAIN;
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guc->fw.load_status = INTEL_UC_FIRMWARE_SUCCESS;
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intel_guc_auth_huc(dev_priv);
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if (i915.enable_guc_submission) {
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if (i915.guc_log_level >= 0)
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gen9_enable_guc_interrupts(dev_priv);
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err = i915_guc_submission_enable(dev_priv);
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if (err)
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goto fail;
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}
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DRM_INFO("GuC %s (firmware %s [version %u.%u])\n",
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i915.enable_guc_submission ? "submission enabled" : "loaded",
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guc->fw.path,
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guc->fw.major_ver_found, guc->fw.minor_ver_found);
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return 0;
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fail:
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if (guc->fw.load_status == INTEL_UC_FIRMWARE_PENDING)
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guc->fw.load_status = INTEL_UC_FIRMWARE_FAIL;
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i915_guc_submission_disable(dev_priv);
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i915_guc_submission_fini(dev_priv);
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i915_ggtt_disable_guc(dev_priv);
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/*
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* We've failed to load the firmware :(
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*
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* Decide whether to disable GuC submission and fall back to
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* execlist mode, and whether to hide the error by returning
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* zero or to return -EIO, which the caller will treat as a
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* nonfatal error (i.e. it doesn't prevent driver load, but
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* marks the GPU as wedged until reset).
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*/
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if (i915.enable_guc_loading > 1) {
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ret = -EIO;
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} else if (i915.enable_guc_submission > 1) {
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ret = -EIO;
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} else {
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ret = 0;
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}
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if (err == 0 && !HAS_GUC_UCODE(dev_priv))
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; /* Don't mention the GuC! */
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else if (err == 0)
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DRM_INFO("GuC firmware load skipped\n");
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else if (ret != -EIO)
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DRM_NOTE("GuC firmware load failed: %d\n", err);
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else
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DRM_WARN("GuC firmware load failed: %d\n", err);
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if (i915.enable_guc_submission) {
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if (fw_path == NULL)
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DRM_INFO("GuC submission without firmware not supported\n");
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if (ret == 0)
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DRM_NOTE("Falling back from GuC submission to execlist mode\n");
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else
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DRM_ERROR("GuC init failed: %d\n", ret);
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}
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i915.enable_guc_submission = 0;
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return ret;
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}
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@ -26,6 +26,27 @@
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#include "intel_uc.h"
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#include <linux/firmware.h>
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/* Reset GuC providing us with fresh state for both GuC and HuC.
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*/
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static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
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{
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int ret;
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u32 guc_status;
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ret = intel_guc_reset(dev_priv);
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if (ret) {
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DRM_ERROR("GuC reset failed, ret = %d\n", ret);
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return ret;
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}
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guc_status = I915_READ(GUC_STATUS);
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WARN(!(guc_status & GS_MIA_IN_RESET),
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"GuC status: 0x%x, MIA core expected to be in reset\n",
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guc_status);
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return ret;
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}
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void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
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{
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if (!HAS_GUC(dev_priv)) {
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@ -63,6 +84,96 @@ void intel_uc_init_fw(struct drm_i915_private *dev_priv)
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intel_guc_init_fw(&dev_priv->guc);
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}
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int intel_uc_init_hw(struct drm_i915_private *dev_priv)
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{
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int ret, attempts;
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/* GuC not enabled, nothing to do */
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if (!i915.enable_guc_loading)
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return 0;
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gen9_reset_guc_interrupts(dev_priv);
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/* We need to notify the guc whenever we change the GGTT */
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i915_ggtt_enable_guc(dev_priv);
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if (i915.enable_guc_submission) {
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ret = i915_guc_submission_init(dev_priv);
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if (ret)
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goto err;
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}
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/* WaEnableuKernelHeaderValidFix:skl */
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/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
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if (IS_GEN9(dev_priv))
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attempts = 3;
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else
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attempts = 1;
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while (attempts--) {
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/*
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* Always reset the GuC just before (re)loading, so
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* that the state and timing are fairly predictable
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*/
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ret = __intel_uc_reset_hw(dev_priv);
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if (ret)
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goto err_submission;
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intel_huc_init_hw(&dev_priv->huc);
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ret = intel_guc_init_hw(&dev_priv->guc);
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if (ret == 0 || ret != -EAGAIN)
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break;
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DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
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"retry %d more time(s)\n", ret, attempts);
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}
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/* Did we succeded or run out of retries? */
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if (ret)
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goto err_submission;
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intel_guc_auth_huc(dev_priv);
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if (i915.enable_guc_submission) {
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if (i915.guc_log_level >= 0)
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gen9_enable_guc_interrupts(dev_priv);
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ret = i915_guc_submission_enable(dev_priv);
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if (ret)
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goto err_submission;
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}
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return 0;
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/*
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* We've failed to load the firmware :(
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*
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* Decide whether to disable GuC submission and fall back to
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* execlist mode, and whether to hide the error by returning
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* zero or to return -EIO, which the caller will treat as a
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* nonfatal error (i.e. it doesn't prevent driver load, but
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* marks the GPU as wedged until reset).
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*/
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err_submission:
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if (i915.enable_guc_submission)
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i915_guc_submission_fini(dev_priv);
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err:
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i915_ggtt_disable_guc(dev_priv);
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DRM_ERROR("GuC init failed\n");
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if (i915.enable_guc_loading > 1 || i915.enable_guc_submission > 1)
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ret = -EIO;
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else
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ret = 0;
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if (i915.enable_guc_submission) {
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i915.enable_guc_submission = 0;
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DRM_NOTE("Falling back from GuC submission to execlist mode\n");
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}
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return ret;
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}
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/*
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* Read GuC command/status register (SOFT_SCRATCH_0)
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* Return true if it contains a response rather than a command
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@ -187,6 +187,7 @@ struct intel_huc {
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void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
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void intel_uc_init_early(struct drm_i915_private *dev_priv);
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void intel_uc_init_fw(struct drm_i915_private *dev_priv);
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int intel_uc_init_hw(struct drm_i915_private *dev_priv);
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void intel_uc_prepare_fw(struct drm_i915_private *dev_priv,
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struct intel_uc_fw *uc_fw);
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int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len);
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