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ARM: dts: sun6i: Add device nodes for first display pipeline 

The A31 has 2 parallel display pipelines, which can be intermixed.
However the driver currently only supports one of them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai 2016-10-20 11:43:42 +08:00 committed by Maxime Ripard
parent f19802bd4d
commit 6d0e5b70be
2 changed files with 160 additions and 0 deletions
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152
arch/arm/boot/dts/sun6i-a31.dtsi
View File

@ -231,6 +231,11 @@ gmac_tx_clk: clk@01c200d0 {
};
};
de: display-engine {
compatible = "allwinner,sun6i-a31-display-engine";
allwinner,pipelines = <&fe0>;
};
soc@01c00000 {
compatible = "simple-bus";
#address-cells = <1>;
@ -246,6 +251,44 @@ dma: dma-controller@01c02000 {
#dma-cells = <1>;
};
tcon0: lcd-controller@01c0c000 {
compatible = "allwinner,sun6i-a31-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ccu RST_AHB1_LCD0>;
reset-names = "lcd";
clocks = <&ccu CLK_AHB1_LCD0>,
<&ccu CLK_LCD0_CH0>,
<&ccu CLK_LCD0_CH1>;
clock-names = "ahb",
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon0-pixel-clock";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tcon0_in_drc0: endpoint@0 {
reg = <0>;
remote-endpoint = <&drc0_out_tcon0>;
};
};
tcon0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
@ -799,6 +842,115 @@ gic: interrupt-controller@01c81000 {
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
fe0: display-frontend@01e00000 {
compatible = "allwinner,sun6i-a31-display-frontend";
reg = <0x01e00000 0x20000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
<&ccu CLK_DRAM_FE0>;
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_AHB1_FE0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
fe0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
fe0_out_be0: endpoint@0 {
reg = <0>;
remote-endpoint = <&be0_in_fe0>;
};
};
};
};
be0: display-backend@01e60000 {
compatible = "allwinner,sun6i-a31-display-backend";
reg = <0x01e60000 0x10000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
<&ccu CLK_DRAM_BE0>;
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_AHB1_BE0>;
assigned-clocks = <&ccu CLK_BE0>;
assigned-clock-rates = <300000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
be0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
be0_in_fe0: endpoint@0 {
reg = <0>;
remote-endpoint = <&fe0_out_be0>;
};
};
be0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
be0_out_drc0: endpoint@0 {
reg = <0>;
remote-endpoint = <&drc0_in_be0>;
};
};
};
};
drc0: drc@01e70000 {
compatible = "allwinner,sun6i-a31-drc";
reg = <0x01e70000 0x10000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
<&ccu CLK_DRAM_DRC0>;
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_AHB1_DRC0>;
assigned-clocks = <&ccu CLK_IEP_DRC0>;
assigned-clock-rates = <300000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
drc0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
drc0_in_be0: endpoint@0 {
reg = <0>;
remote-endpoint = <&be0_out_drc0>;
};
};
drc0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
drc0_out_tcon0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon0_in_drc0>;
};
};
};
};
rtc: rtc@01f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;

8
arch/arm/boot/dts/sun6i-a31s.dtsi
View File

@ -48,6 +48,14 @@
#include "sun6i-a31.dtsi"
&de {
compatible = "allwinner,sun6i-a31s-display-engine";
};
&pio {
compatible = "allwinner,sun6i-a31s-pinctrl";
};
&tcon0 {
compatible = "allwinner,sun6i-a31s-tcon";
};