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drm/nouveau/fb: read TILE_BASE after writing it to avoid a hardware race 

Apparently needed for turbocache nv4x chips at least, we'll just do it
everywhere...

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2012-10-10 11:09:48 +10:00
parent 5f8e256704
commit 6d338081a6
4 changed files with 4 additions and 0 deletions
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1
drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c
View File

@ -54,6 +54,7 @@ nv10_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit); nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch); nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch);
nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr); nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr);
nv_rd32(pfb, 0x100240 + (i * 0x10));
} }
static int static int

1
drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c
View File

@ -83,6 +83,7 @@ nv20_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit); nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch); nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch);
nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr); nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr);
nv_rd32(pfb, 0x100240 + (i * 0x10));
nv_wr32(pfb, 0x100300 + (i * 0x04), tile->zcomp); nv_wr32(pfb, 0x100300 + (i * 0x04), tile->zcomp);
} }

1
drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c
View File

@ -36,6 +36,7 @@ nv41_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr); nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
nv_rd32(pfb, 0x100600 + (i * 0x10));
nv_wr32(pfb, 0x100700 + (i * 0x04), tile->zcomp); nv_wr32(pfb, 0x100700 + (i * 0x04), tile->zcomp);
} }

1
drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c
View File

@ -46,6 +46,7 @@ nv44_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr); nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
nv_rd32(pfb, 0x100600 + (i * 0x10));
} }
int int