mirror of https://gitee.com/openkylin/linux.git
net: hns3: Add enable and process common ecc errors
This patch adds enable and processing of ecc errors from common HNS blocks, CMDQ(Command Queue), IMP(Integrated Management Processor) and TQP(Task Queue Pair). Signed-off-by: Shiju Jose <shiju.jose@huawei.com> Signed-off-by: Salil Mehta <salil.mehta@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Shiju Jose
David S. Miller
parent
9971419503
commit
6d67ee9a27
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@ -209,6 +209,9 @@ enum hclge_opcode_type {
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/* Led command */
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HCLGE_OPC_LED_STATUS_CFG = 0xB000,
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/* Error INT commands */
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HCLGE_COMMON_ECC_INT_CFG = 0x1505,
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};
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#define HCLGE_TQP_REG_OFFSET 0x80000
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@ -3,7 +3,292 @@
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#include "hclge_err.h"
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static const struct hclge_hw_error hclge_imp_tcm_ecc_int[] = {
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{ .int_msk = BIT(0), .msg = "imp_itcm0_ecc_1bit_err" },
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{ .int_msk = BIT(1), .msg = "imp_itcm0_ecc_mbit_err" },
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{ .int_msk = BIT(2), .msg = "imp_itcm1_ecc_1bit_err" },
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{ .int_msk = BIT(3), .msg = "imp_itcm1_ecc_mbit_err" },
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{ .int_msk = BIT(4), .msg = "imp_itcm2_ecc_1bit_err" },
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{ .int_msk = BIT(5), .msg = "imp_itcm2_ecc_mbit_err" },
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{ .int_msk = BIT(6), .msg = "imp_itcm3_ecc_1bit_err" },
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{ .int_msk = BIT(7), .msg = "imp_itcm3_ecc_mbit_err" },
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{ .int_msk = BIT(8), .msg = "imp_dtcm0_mem0_ecc_1bit_err" },
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{ .int_msk = BIT(9), .msg = "imp_dtcm0_mem0_ecc_mbit_err" },
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{ .int_msk = BIT(10), .msg = "imp_dtcm0_mem1_ecc_1bit_err" },
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{ .int_msk = BIT(11), .msg = "imp_dtcm0_mem1_ecc_mbit_err" },
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{ .int_msk = BIT(12), .msg = "imp_dtcm1_mem0_ecc_1bit_err" },
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{ .int_msk = BIT(13), .msg = "imp_dtcm1_mem0_ecc_mbit_err" },
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{ .int_msk = BIT(14), .msg = "imp_dtcm1_mem1_ecc_1bit_err" },
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{ .int_msk = BIT(15), .msg = "imp_dtcm1_mem1_ecc_mbit_err" },
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{ /* sentinel */ }
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};
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static const struct hclge_hw_error hclge_imp_itcm4_ecc_int[] = {
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{ .int_msk = BIT(0), .msg = "imp_itcm4_ecc_1bit_err" },
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{ .int_msk = BIT(1), .msg = "imp_itcm4_ecc_mbit_err" },
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{ /* sentinel */ }
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};
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static const struct hclge_hw_error hclge_cmdq_nic_mem_ecc_int[] = {
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{ .int_msk = BIT(0), .msg = "cmdq_nic_rx_depth_ecc_1bit_err" },
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{ .int_msk = BIT(1), .msg = "cmdq_nic_rx_depth_ecc_mbit_err" },
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{ .int_msk = BIT(2), .msg = "cmdq_nic_tx_depth_ecc_1bit_err" },
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{ .int_msk = BIT(3), .msg = "cmdq_nic_tx_depth_ecc_mbit_err" },
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{ .int_msk = BIT(4), .msg = "cmdq_nic_rx_tail_ecc_1bit_err" },
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{ .int_msk = BIT(5), .msg = "cmdq_nic_rx_tail_ecc_mbit_err" },
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{ .int_msk = BIT(6), .msg = "cmdq_nic_tx_tail_ecc_1bit_err" },
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{ .int_msk = BIT(7), .msg = "cmdq_nic_tx_tail_ecc_mbit_err" },
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{ .int_msk = BIT(8), .msg = "cmdq_nic_rx_head_ecc_1bit_err" },
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{ .int_msk = BIT(9), .msg = "cmdq_nic_rx_head_ecc_mbit_err" },
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{ .int_msk = BIT(10), .msg = "cmdq_nic_tx_head_ecc_1bit_err" },
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{ .int_msk = BIT(11), .msg = "cmdq_nic_tx_head_ecc_mbit_err" },
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{ .int_msk = BIT(12), .msg = "cmdq_nic_rx_addr_ecc_1bit_err" },
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{ .int_msk = BIT(13), .msg = "cmdq_nic_rx_addr_ecc_mbit_err" },
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{ .int_msk = BIT(14), .msg = "cmdq_nic_tx_addr_ecc_1bit_err" },
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{ .int_msk = BIT(15), .msg = "cmdq_nic_tx_addr_ecc_mbit_err" },
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{ /* sentinel */ }
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};
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static const struct hclge_hw_error hclge_cmdq_rocee_mem_ecc_int[] = {
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{ .int_msk = BIT(0), .msg = "cmdq_rocee_rx_depth_ecc_1bit_err" },
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{ .int_msk = BIT(1), .msg = "cmdq_rocee_rx_depth_ecc_mbit_err" },
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{ .int_msk = BIT(2), .msg = "cmdq_rocee_tx_depth_ecc_1bit_err" },
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{ .int_msk = BIT(3), .msg = "cmdq_rocee_tx_depth_ecc_mbit_err" },
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{ .int_msk = BIT(4), .msg = "cmdq_rocee_rx_tail_ecc_1bit_err" },
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{ .int_msk = BIT(5), .msg = "cmdq_rocee_rx_tail_ecc_mbit_err" },
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{ .int_msk = BIT(6), .msg = "cmdq_rocee_tx_tail_ecc_1bit_err" },
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{ .int_msk = BIT(7), .msg = "cmdq_rocee_tx_tail_ecc_mbit_err" },
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{ .int_msk = BIT(8), .msg = "cmdq_rocee_rx_head_ecc_1bit_err" },
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{ .int_msk = BIT(9), .msg = "cmdq_rocee_rx_head_ecc_mbit_err" },
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{ .int_msk = BIT(10), .msg = "cmdq_rocee_tx_head_ecc_1bit_err" },
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{ .int_msk = BIT(11), .msg = "cmdq_rocee_tx_head_ecc_mbit_err" },
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{ .int_msk = BIT(12), .msg = "cmdq_rocee_rx_addr_ecc_1bit_err" },
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{ .int_msk = BIT(13), .msg = "cmdq_rocee_rx_addr_ecc_mbit_err" },
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{ .int_msk = BIT(14), .msg = "cmdq_rocee_tx_addr_ecc_1bit_err" },
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{ .int_msk = BIT(15), .msg = "cmdq_rocee_tx_addr_ecc_mbit_err" },
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{ /* sentinel */ }
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};
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static const struct hclge_hw_error hclge_tqp_int_ecc_int[] = {
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{ .int_msk = BIT(0), .msg = "tqp_int_cfg_even_ecc_1bit_err" },
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{ .int_msk = BIT(1), .msg = "tqp_int_cfg_odd_ecc_1bit_err" },
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{ .int_msk = BIT(2), .msg = "tqp_int_ctrl_even_ecc_1bit_err" },
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{ .int_msk = BIT(3), .msg = "tqp_int_ctrl_odd_ecc_1bit_err" },
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{ .int_msk = BIT(4), .msg = "tx_que_scan_int_ecc_1bit_err" },
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{ .int_msk = BIT(5), .msg = "rx_que_scan_int_ecc_1bit_err" },
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{ .int_msk = BIT(6), .msg = "tqp_int_cfg_even_ecc_mbit_err" },
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{ .int_msk = BIT(7), .msg = "tqp_int_cfg_odd_ecc_mbit_err" },
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{ .int_msk = BIT(8), .msg = "tqp_int_ctrl_even_ecc_mbit_err" },
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{ .int_msk = BIT(9), .msg = "tqp_int_ctrl_odd_ecc_mbit_err" },
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{ .int_msk = BIT(10), .msg = "tx_que_scan_int_ecc_mbit_err" },
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{ .int_msk = BIT(11), .msg = "rx_que_scan_int_ecc_mbit_err" },
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{ /* sentinel */ }
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};
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static void hclge_log_error(struct device *dev,
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const struct hclge_hw_error *err_list,
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u32 err_sts)
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{
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const struct hclge_hw_error *err;
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int i = 0;
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while (err_list[i].msg) {
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err = &err_list[i];
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if (!(err->int_msk & err_sts)) {
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i++;
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continue;
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}
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dev_warn(dev, "%s [error status=0x%x] found\n",
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err->msg, err_sts);
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i++;
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}
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}
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/* hclge_cmd_query_error: read the error information
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* @hdev: pointer to struct hclge_dev
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* @desc: descriptor for describing the command
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* @cmd: command opcode
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* @flag: flag for extended command structure
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* @w_num: offset for setting the read interrupt type.
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* @int_type: select which type of the interrupt for which the error
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* info will be read(RAS-CE/RAS-NFE/RAS-FE etc).
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*
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* This function query the error info from hw register/s using command
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*/
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static int hclge_cmd_query_error(struct hclge_dev *hdev,
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struct hclge_desc *desc, u32 cmd,
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u16 flag, u8 w_num,
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enum hclge_err_int_type int_type)
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{
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struct device *dev = &hdev->pdev->dev;
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int num = 1;
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int ret;
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hclge_cmd_setup_basic_desc(&desc[0], cmd, true);
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if (flag) {
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desc[0].flag |= cpu_to_le16(flag);
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hclge_cmd_setup_basic_desc(&desc[1], cmd, true);
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num = 2;
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}
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if (w_num)
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desc[0].data[w_num] = cpu_to_le32(int_type);
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ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
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if (ret)
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dev_err(dev, "query error cmd failed (%d)\n", ret);
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return ret;
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}
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/* hclge_cmd_clear_error: clear the error status
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* @hdev: pointer to struct hclge_dev
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* @desc: descriptor for describing the command
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* @desc_src: prefilled descriptor from the previous command for reusing
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* @cmd: command opcode
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* @flag: flag for extended command structure
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*
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* This function clear the error status in the hw register/s using command
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*/
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static int hclge_cmd_clear_error(struct hclge_dev *hdev,
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struct hclge_desc *desc,
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struct hclge_desc *desc_src,
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u32 cmd, u16 flag)
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{
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struct device *dev = &hdev->pdev->dev;
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int num = 1;
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int ret, i;
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if (cmd) {
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hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
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if (flag) {
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desc[0].flag |= cpu_to_le16(flag);
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hclge_cmd_setup_basic_desc(&desc[1], cmd, false);
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num = 2;
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}
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if (desc_src) {
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for (i = 0; i < 6; i++) {
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desc[0].data[i] = desc_src[0].data[i];
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if (flag)
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desc[1].data[i] = desc_src[1].data[i];
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}
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}
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} else {
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hclge_cmd_reuse_desc(&desc[0], false);
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if (flag) {
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desc[0].flag |= cpu_to_le16(flag);
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hclge_cmd_reuse_desc(&desc[1], false);
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num = 2;
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}
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}
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ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
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if (ret)
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dev_err(dev, "clear error cmd failed (%d)\n", ret);
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return ret;
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}
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static int hclge_enable_common_error(struct hclge_dev *hdev, bool en)
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{
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struct device *dev = &hdev->pdev->dev;
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struct hclge_desc desc[2];
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int ret;
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hclge_cmd_setup_basic_desc(&desc[0], HCLGE_COMMON_ECC_INT_CFG, false);
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desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
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hclge_cmd_setup_basic_desc(&desc[1], HCLGE_COMMON_ECC_INT_CFG, false);
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if (en) {
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/* enable COMMON error interrupts */
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desc[0].data[0] = cpu_to_le32(HCLGE_IMP_TCM_ECC_ERR_INT_EN);
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desc[0].data[2] = cpu_to_le32(HCLGE_CMDQ_NIC_ECC_ERR_INT_EN |
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HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN);
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desc[0].data[3] = cpu_to_le32(HCLGE_IMP_RD_POISON_ERR_INT_EN);
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desc[0].data[4] = cpu_to_le32(HCLGE_TQP_ECC_ERR_INT_EN);
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desc[0].data[5] = cpu_to_le32(HCLGE_IMP_ITCM4_ECC_ERR_INT_EN);
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} else {
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/* disable COMMON error interrupts */
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desc[0].data[0] = 0;
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desc[0].data[2] = 0;
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desc[0].data[3] = 0;
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desc[0].data[4] = 0;
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desc[0].data[5] = 0;
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}
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desc[1].data[0] = cpu_to_le32(HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK);
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desc[1].data[2] = cpu_to_le32(HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK |
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HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK);
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desc[1].data[3] = cpu_to_le32(HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK);
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desc[1].data[4] = cpu_to_le32(HCLGE_TQP_ECC_ERR_INT_EN_MASK);
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desc[1].data[5] = cpu_to_le32(HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK);
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ret = hclge_cmd_send(&hdev->hw, &desc[0], 2);
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if (ret)
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dev_err(dev,
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"failed(%d) to enable/disable COMMON err interrupts\n",
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ret);
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return ret;
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}
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static void hclge_process_common_error(struct hclge_dev *hdev,
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enum hclge_err_int_type type)
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{
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struct device *dev = &hdev->pdev->dev;
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struct hclge_desc desc[2];
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u32 err_sts;
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int ret;
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/* read err sts */
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ret = hclge_cmd_query_error(hdev, &desc[0],
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HCLGE_COMMON_ECC_INT_CFG,
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HCLGE_CMD_FLAG_NEXT, 0, 0);
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if (ret) {
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dev_err(dev,
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"failed(=%d) to query COMMON error interrupt status\n",
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ret);
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return;
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}
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/* log err */
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err_sts = (le32_to_cpu(desc[0].data[0])) & HCLGE_IMP_TCM_ECC_INT_MASK;
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hclge_log_error(dev, &hclge_imp_tcm_ecc_int[0], err_sts);
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err_sts = (le32_to_cpu(desc[0].data[1])) & HCLGE_CMDQ_ECC_INT_MASK;
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hclge_log_error(dev, &hclge_cmdq_nic_mem_ecc_int[0], err_sts);
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err_sts = (le32_to_cpu(desc[0].data[1]) >> HCLGE_CMDQ_ROC_ECC_INT_SHIFT)
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& HCLGE_CMDQ_ECC_INT_MASK;
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hclge_log_error(dev, &hclge_cmdq_rocee_mem_ecc_int[0], err_sts);
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if ((le32_to_cpu(desc[0].data[3])) & BIT(0))
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dev_warn(dev, "imp_rd_data_poison_err found\n");
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err_sts = (le32_to_cpu(desc[0].data[3]) >> HCLGE_TQP_ECC_INT_SHIFT) &
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HCLGE_TQP_ECC_INT_MASK;
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hclge_log_error(dev, &hclge_tqp_int_ecc_int[0], err_sts);
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err_sts = (le32_to_cpu(desc[0].data[5])) &
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HCLGE_IMP_ITCM4_ECC_INT_MASK;
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hclge_log_error(dev, &hclge_imp_itcm4_ecc_int[0], err_sts);
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/* clear error interrupts */
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desc[1].data[0] = cpu_to_le32(HCLGE_IMP_TCM_ECC_CLR_MASK);
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desc[1].data[1] = cpu_to_le32(HCLGE_CMDQ_NIC_ECC_CLR_MASK |
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HCLGE_CMDQ_ROCEE_ECC_CLR_MASK);
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desc[1].data[3] = cpu_to_le32(HCLGE_TQP_IMP_ERR_CLR_MASK);
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desc[1].data[5] = cpu_to_le32(HCLGE_IMP_ITCM4_ECC_CLR_MASK);
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ret = hclge_cmd_clear_error(hdev, &desc[0], NULL, 0,
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HCLGE_CMD_FLAG_NEXT);
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if (ret)
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dev_err(dev,
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"failed(%d) to clear COMMON error interrupt status\n",
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ret);
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}
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static const struct hclge_hw_blk hw_blk[] = {
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{ .msk = BIT(5), .name = "COMMON",
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.enable_error = hclge_enable_common_error,
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.process_error = hclge_process_common_error, },
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{ /* sentinel */ }
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};
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@ -11,6 +11,31 @@
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#define HCLGE_RAS_REG_NFE_MASK 0xFF00
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#define HCLGE_RAS_REG_NFE_SHIFT 8
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#define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
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#define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
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#define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300
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#define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300
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#define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF
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#define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF
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#define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN 0xFFFF0000
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#define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK 0xFFFF0000
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#define HCLGE_IMP_RD_POISON_ERR_INT_EN 0x0100
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#define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100
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#define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF
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#define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
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#define HCLGE_IMP_TCM_ECC_INT_MASK 0xFFFF
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#define HCLGE_IMP_ITCM4_ECC_INT_MASK 0x3
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#define HCLGE_CMDQ_ECC_INT_MASK 0xFFFF
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#define HCLGE_CMDQ_ROC_ECC_INT_SHIFT 16
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#define HCLGE_TQP_ECC_INT_MASK 0xFFF
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||||
#define HCLGE_TQP_ECC_INT_SHIFT 16
|
||||
#define HCLGE_IMP_TCM_ECC_CLR_MASK 0xFFFF
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||||
#define HCLGE_IMP_ITCM4_ECC_CLR_MASK 0x3
|
||||
#define HCLGE_CMDQ_NIC_ECC_CLR_MASK 0xFFFF
|
||||
#define HCLGE_CMDQ_ROCEE_ECC_CLR_MASK 0xFFFF0000
|
||||
#define HCLGE_TQP_IMP_ERR_CLR_MASK 0x0FFF0001
|
||||
|
||||
enum hclge_err_int_type {
|
||||
HCLGE_ERR_INT_MSIX = 0,
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HCLGE_ERR_INT_RAS_CE = 1,
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||||
|
|
@ -26,6 +51,11 @@ struct hclge_hw_blk {
|
|||
enum hclge_err_int_type type);
|
||||
};
|
||||
|
||||
struct hclge_hw_error {
|
||||
u32 int_msk;
|
||||
const char *msg;
|
||||
};
|
||||
|
||||
int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state);
|
||||
pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue