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Board-level changes 

This adds and extends support for specific boards on a number of
 ARM platforms:  omap, imx, samsung, tegra, ...
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Merge tag 'boards' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Board-level changes

This adds and extends support for specific boards on a number of
ARM platforms:  omap, imx, samsung, tegra, ...

* tag 'boards' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (49 commits)
  Enable 32 bit flash support for iMX21ADS board
  ARM: mx31pdk: Add MC13783 RTC support
  iomux-mx25: configuration to support CSPI3 on CSI pins
  MX1:apf9328: Add i2c support
  mioa701: add newly available DoC G3 chip
  arm/tegra: remove __initdata annotation from pinmux tables
  arm/tegra: Use bus notifiers to trigger pinmux setup
  arm/tegra: Refactor board-*-pinmux.c to share code
  arm/tegra: Fix mistake in Trimslice's pinmux
  arm/tegra: Rework Seaboard-vs-Ventana pinmux table
  arm/tegra: Remove useless entries from ventana_pinmux[]
  arm/tegra: PCIe: Remove include of mach/pinmux.h
  arm/tegra: Harmony PCIe: Don't touch pinmux
  arm/tegra: Add AUXDATA for tegra-pinmux and tegra-gpio
  arm/tegra: Split Seaboard GPIO table to allow for Ventana
  ARM: imx6q: generate imx6q dtb files
  arm/imx6q: Rename Sabreauto to Armadillo2
  arm/imx6q-sabrelite: add enet phy ksz9021rn fixup
  arm/imx6: add imx6q sabrelite board support
  dts/imx: rename uart labels to consistent with hw spec
  ...
This commit is contained in:
Linus Torvalds 2012-01-09 14:37:41 -08:00
parent 7400c12eb0 421b759b86
commit 6d889d03ab
52 changed files with 876 additions and 286 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/arm/fsl.txt
View File

@ -21,6 +21,10 @@ i.MX53 Smart Mobile Reference Design Board
Required root node properties:
- compatible = "fsl,imx53-smd", "fsl,imx53";
i.MX6 Quad SABRE Automotive Board
i.MX6 Quad Armadillo2 Board
Required root node properties:
- compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
- compatible = "fsl,imx6q-arm2", "fsl,imx6q";
i.MX6 Quad SABRE Lite Board
Required root node properties:
- compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";

17
arch/arm/boot/dts/imx51-babbage.dts
View File

@ -35,20 +35,19 @@ esdhc@70004000 { /* ESDHC1 */
};
esdhc@70008000 { /* ESDHC2 */
cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */
wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */
cd-gpios = <&gpio1 6 0>;
wp-gpios = <&gpio1 5 0>;
status = "okay";
};
uart2: uart@7000c000 { /* UART3 */
uart3: uart@7000c000 {
fsl,uart-has-rtscts;
status = "okay";
};
ecspi@70010000 { /* ECSPI1 */
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
<&gpio3 25 0>; /* GPIO4_25 */
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
status = "okay";
pmic: mc13892@0 {
@ -57,7 +56,7 @@ pmic: mc13892@0 {
compatible = "fsl,mc13892";
spi-max-frequency = <6000000>;
reg = <0>;
mc13xxx-irq-gpios = <&gpio0 8 0>; /* GPIO1_8 */
mc13xxx-irq-gpios = <&gpio1 8 0>;
fsl,mc13xxx-uses-regulator;
};
@ -91,12 +90,12 @@ iomuxc@73fa8000 {
reg = <0x73fa8000 0x4000>;
};
uart0: uart@73fbc000 {
uart1: uart@73fbc000 {
fsl,uart-has-rtscts;
status = "okay";
};
uart1: uart@73fc0000 {
uart2: uart@73fc0000 {
status = "okay";
};
};
@ -127,7 +126,7 @@ gpio-keys {
power {
label = "Power Button";
gpios = <&gpio1 21 0>;
gpios = <&gpio2 21 0>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};

20
arch/arm/boot/dts/imx51.dtsi
View File

@ -14,9 +14,9 @@
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
};
tzic: tz-interrupt-controller@e0000000 {
@ -86,7 +86,7 @@ esdhc@70008000 { /* ESDHC2 */
status = "disabled";
};
uart2: uart@7000c000 { /* UART3 */
uart3: uart@7000c000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x7000c000 0x4000>;
interrupts = <33>;
@ -117,7 +117,7 @@ esdhc@70024000 { /* ESDHC4 */
};
};
gpio0: gpio@73f84000 { /* GPIO1 */
gpio1: gpio@73f84000 {
compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
reg = <0x73f84000 0x4000>;
interrupts = <50 51>;
@ -127,7 +127,7 @@ gpio0: gpio@73f84000 { /* GPIO1 */
#interrupt-cells = <1>;
};
gpio1: gpio@73f88000 { /* GPIO2 */
gpio2: gpio@73f88000 {
compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
reg = <0x73f88000 0x4000>;
interrupts = <52 53>;
@ -137,7 +137,7 @@ gpio1: gpio@73f88000 { /* GPIO2 */
#interrupt-cells = <1>;
};
gpio2: gpio@73f8c000 { /* GPIO3 */
gpio3: gpio@73f8c000 {
compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
reg = <0x73f8c000 0x4000>;
interrupts = <54 55>;
@ -147,7 +147,7 @@ gpio2: gpio@73f8c000 { /* GPIO3 */
#interrupt-cells = <1>;
};
gpio3: gpio@73f90000 { /* GPIO4 */
gpio4: gpio@73f90000 {
compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
reg = <0x73f90000 0x4000>;
interrupts = <56 57>;
@ -171,14 +171,14 @@ wdog@73f9c000 { /* WDOG2 */
status = "disabled";
};
uart0: uart@73fbc000 {
uart1: uart@73fbc000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
status = "disabled";
};
uart1: uart@73fc0000 {
uart2: uart@73fc0000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fc0000 0x4000>;
interrupts = <32>;

18
arch/arm/boot/dts/imx53-ard.dts
View File

@ -29,8 +29,8 @@ soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
cd-gpios = <&gpio0 1 0>; /* GPIO1_1 */
wp-gpios = <&gpio0 9 0>; /* GPIO1_9 */
cd-gpios = <&gpio1 1 0>;
wp-gpios = <&gpio1 9 0>;
status = "okay";
};
};
@ -44,7 +44,7 @@ iomuxc@53fa8000 {
reg = <0x53fa8000 0x4000>;
};
uart0: uart@53fbc000 { /* UART1 */
uart1: uart@53fbc000 {
status = "okay";
};
};
@ -67,7 +67,7 @@ lan9220@f4000000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0xf4000000 0x2000000>;
phy-mode = "mii";
interrupt-parent = <&gpio1>;
interrupt-parent = <&gpio2>;
interrupts = <31>;
reg-io-width = <4>;
smsc,irq-push-pull;
@ -79,34 +79,34 @@ gpio-keys {
home {
label = "Home";
gpios = <&gpio4 10 0>; /* GPIO5_10 */
gpios = <&gpio5 10 0>;
linux,code = <102>; /* KEY_HOME */
gpio-key,wakeup;
};
back {
label = "Back";
gpios = <&gpio4 11 0>; /* GPIO5_11 */
gpios = <&gpio5 11 0>;
linux,code = <158>; /* KEY_BACK */
gpio-key,wakeup;
};
program {
label = "Program";
gpios = <&gpio4 12 0>; /* GPIO5_12 */
gpios = <&gpio5 12 0>;
linux,code = <362>; /* KEY_PROGRAM */
gpio-key,wakeup;
};
volume-up {
label = "Volume Up";
gpios = <&gpio4 13 0>; /* GPIO5_13 */
gpios = <&gpio5 13 0>;
linux,code = <115>; /* KEY_VOLUMEUP */
};
volume-down {
label = "Volume Down";
gpios = <&gpio3 0 0>; /* GPIO4_0 */
gpios = <&gpio4 0 0>;
linux,code = <114>; /* KEY_VOLUMEDOWN */
};
};

17
arch/arm/boot/dts/imx53-evk.dts
View File

@ -29,15 +29,14 @@ soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
wp-gpios = <&gpio2 14 0>; /* GPIO3_14 */
cd-gpios = <&gpio3 13 0>;
wp-gpios = <&gpio3 14 0>;
status = "okay";
};
ecspi@50010000 { /* ECSPI1 */
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
<&gpio2 19 0>; /* GPIO3_19 */
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
flash: at45db321d@1 {
@ -61,8 +60,8 @@ partition@40000 {
};
esdhc@50020000 { /* ESDHC3 */
cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
};
@ -76,7 +75,7 @@ iomuxc@53fa8000 {
reg = <0x53fa8000 0x4000>;
};
uart0: uart@53fbc000 { /* UART1 */
uart1: uart@53fbc000 {
status = "okay";
};
};
@ -102,7 +101,7 @@ codec: sgtl5000@0a {
fec@63fec000 {
phy-mode = "rmii";
phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};
};
@ -113,7 +112,7 @@ leds {
green {
label = "Heartbeat";
gpios = <&gpio6 7 0>; /* GPIO7_7 */
gpios = <&gpio7 7 0>;
linux,default-trigger = "heartbeat";
};
};

18
arch/arm/boot/dts/imx53-qsb.dts
View File

@ -29,13 +29,13 @@ soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
cd-gpios = <&gpio3 13 0>;
status = "okay";
};
esdhc@50020000 { /* ESDHC3 */
cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
};
@ -49,7 +49,7 @@ iomuxc@53fa8000 {
reg = <0x53fa8000 0x4000>;
};
uart0: uart@53fbc000 { /* UART1 */
uart1: uart@53fbc000 {
status = "okay";
};
};
@ -84,7 +84,7 @@ pmic: dialog@48 {
fec@63fec000 {
phy-mode = "rmii";
phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};
};
@ -95,20 +95,20 @@ gpio-keys {
power {
label = "Power Button";
gpios = <&gpio0 8 0>; /* GPIO1_8 */
gpios = <&gpio1 8 0>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
volume-up {
label = "Volume Up";
gpios = <&gpio1 14 0>; /* GPIO2_14 */
gpios = <&gpio2 14 0>;
linux,code = <115>; /* KEY_VOLUMEUP */
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 15 0>; /* GPIO2_15 */
gpios = <&gpio2 15 0>;
linux,code = <114>; /* KEY_VOLUMEDOWN */
};
};
@ -118,7 +118,7 @@ leds {
user {
label = "Heartbeat";
gpios = <&gpio6 7 0>; /* GPIO7_7 */
gpios = <&gpio7 7 0>;
linux,default-trigger = "heartbeat";
};
};

19
arch/arm/boot/dts/imx53-smd.dts
View File

@ -29,8 +29,8 @@ soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
wp-gpios = <&gpio3 11 0>; /* GPIO4_11 */
cd-gpios = <&gpio3 13 0>;
wp-gpios = <&gpio4 11 0>;
status = "okay";
};
@ -39,15 +39,14 @@ esdhc@50008000 { /* ESDHC2 */
status = "okay";
};
uart2: uart@5000c000 { /* UART3 */
uart3: uart@5000c000 {
fsl,uart-has-rtscts;
status = "okay";
};
ecspi@50010000 { /* ECSPI1 */
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
<&gpio2 19 0>; /* GPIO3_19 */
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
zigbee: mc1323@0 {
@ -91,11 +90,11 @@ iomuxc@53fa8000 {
reg = <0x53fa8000 0x4000>;
};
uart0: uart@53fbc000 { /* UART1 */
uart1: uart@53fbc000 {
status = "okay";
};
uart1: uart@53fc0000 { /* UART2 */
uart2: uart@53fc0000 {
status = "okay";
};
};
@ -145,7 +144,7 @@ pmic: dialog@48 {
fec@63fec000 {
phy-mode = "rmii";
phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};
};
@ -156,13 +155,13 @@ gpio-keys {
volume-up {
label = "Volume Up";
gpios = <&gpio1 14 0>; /* GPIO2_14 */
gpios = <&gpio2 14 0>;
linux,code = <115>; /* KEY_VOLUMEUP */
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 15 0>; /* GPIO2_15 */
gpios = <&gpio2 15 0>;
linux,code = <114>; /* KEY_VOLUMEDOWN */
};
};

34
arch/arm/boot/dts/imx53.dtsi
View File

@ -14,11 +14,11 @@
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
};
tzic: tz-interrupt-controller@0fffc000 {
@ -88,7 +88,7 @@ esdhc@50008000 { /* ESDHC2 */
status = "disabled";
};
uart2: uart@5000c000 { /* UART3 */
uart3: uart@5000c000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x5000c000 0x4000>;
interrupts = <33>;
@ -119,7 +119,7 @@ esdhc@50024000 { /* ESDHC4 */
};
};
gpio0: gpio@53f84000 { /* GPIO1 */
gpio1: gpio@53f84000 {
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
reg = <0x53f84000 0x4000>;
interrupts = <50 51>;
@ -129,7 +129,7 @@ gpio0: gpio@53f84000 { /* GPIO1 */
#interrupt-cells = <1>;
};
gpio1: gpio@53f88000 { /* GPIO2 */
gpio2: gpio@53f88000 {
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
reg = <0x53f88000 0x4000>;
interrupts = <52 53>;
@ -139,7 +139,7 @@ gpio1: gpio@53f88000 { /* GPIO2 */
#interrupt-cells = <1>;
};
gpio2: gpio@53f8c000 { /* GPIO3 */
gpio3: gpio@53f8c000 {
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
reg = <0x53f8c000 0x4000>;
interrupts = <54 55>;
@ -149,7 +149,7 @@ gpio2: gpio@53f8c000 { /* GPIO3 */
#interrupt-cells = <1>;
};
gpio3: gpio@53f90000 { /* GPIO4 */
gpio4: gpio@53f90000 {
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
reg = <0x53f90000 0x4000>;
interrupts = <56 57>;
@ -173,21 +173,21 @@ wdog@53f9c000 { /* WDOG2 */
status = "disabled";
};
uart0: uart@53fbc000 { /* UART1 */
uart1: uart@53fbc000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fbc000 0x4000>;
interrupts = <31>;
status = "disabled";
};
uart1: uart@53fc0000 { /* UART2 */
uart2: uart@53fc0000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fc0000 0x4000>;
interrupts = <32>;
status = "disabled";
};
gpio4: gpio@53fdc000 { /* GPIO5 */
gpio5: gpio@53fdc000 {
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
reg = <0x53fdc000 0x4000>;
interrupts = <103 104>;
@ -197,7 +197,7 @@ gpio4: gpio@53fdc000 { /* GPIO5 */
#interrupt-cells = <1>;
};
gpio5: gpio@53fe0000 { /* GPIO6 */
gpio6: gpio@53fe0000 {
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
reg = <0x53fe0000 0x4000>;
interrupts = <105 106>;
@ -207,7 +207,7 @@ gpio5: gpio@53fe0000 { /* GPIO6 */
#interrupt-cells = <1>;
};
gpio6: gpio@53fe4000 { /* GPIO7 */
gpio7: gpio@53fe4000 {
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
reg = <0x53fe4000 0x4000>;
interrupts = <107 108>;
@ -226,7 +226,7 @@ i2c@53fec000 { /* I2C3 */
status = "disabled";
};
uart3: uart@53ff0000 { /* UART4 */
uart4: uart@53ff0000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53ff0000 0x4000>;
interrupts = <13>;
@ -241,7 +241,7 @@ aips@60000000 { /* AIPS2 */
reg = <0x60000000 0x10000000>;
ranges;
uart4: uart@63f90000 { /* UART5 */
uart5: uart@63f90000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x63f90000 0x4000>;
interrupts = <86>;

12
arch/arm/boot/dts/imx6q-sabreauto.dts → arch/arm/boot/dts/imx6q-arm2.dts
View File

@ -14,8 +14,8 @@
/include/ "imx6q.dtsi"
/ {
model = "Freescale i.MX6 Quad SABRE Automotive Board";
compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
model = "Freescale i.MX6 Quad Armadillo2 Board";
compatible = "fsl,imx6q-arm2", "fsl,imx6q";
chosen {
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
@ -34,8 +34,8 @@ enet@02188000 {
};
usdhc@02198000 { /* uSDHC3 */
cd-gpios = <&gpio5 11 0>; /* GPIO6_11 */
wp-gpios = <&gpio5 14 0>; /* GPIO6_14 */
cd-gpios = <&gpio6 11 0>;
wp-gpios = <&gpio6 14 0>;
status = "okay";
};
@ -44,7 +44,7 @@ usdhc@0219c000 { /* uSDHC4 */
status = "okay";
};
uart3: uart@021f0000 { /* UART4 */
uart4: uart@021f0000 {
status = "okay";
};
};
@ -55,7 +55,7 @@ leds {
debug-led {
label = "Heartbeat";
gpios = <&gpio2 25 0>; /* GPIO3_25 */
gpios = <&gpio3 25 0>;
linux,default-trigger = "heartbeat";
};
};

49
arch/arm/boot/dts/imx6q-sabrelite.dts Normal file
View File

@ -0,0 +1,49 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx6q.dtsi"
/ {
model = "Freescale i.MX6 Quad SABRE Lite Board";
compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
memory {
reg = <0x10000000 0x40000000>;
};
soc {
aips-bus@02100000 { /* AIPS2 */
enet@02188000 {
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
cd-gpios = <&gpio7 0 0>;
wp-gpios = <&gpio7 1 0>;
status = "okay";
};
usdhc@0219c000 { /* uSDHC4 */
cd-gpios = <&gpio2 6 0>;
wp-gpios = <&gpio2 7 0>;
status = "okay";
};
uart2: uart@021e8000 {
status = "okay";
};
};
};
};

34
arch/arm/boot/dts/imx6q.dtsi
View File

@ -14,11 +14,11 @@
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
};
cpus {
@ -165,7 +165,7 @@ ecspi@02018000 { /* eCSPI5 */
status = "disabled";
};
uart0: uart@02020000 { /* UART1 */
uart1: uart@02020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
@ -247,7 +247,7 @@ gpt@02098000 {
interrupts = <0 55 0x04>;
};
gpio0: gpio@0209c000 { /* GPIO1 */
gpio1: gpio@0209c000 {
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
reg = <0x0209c000 0x4000>;
interrupts = <0 66 0x04 0 67 0x04>;
@ -257,7 +257,7 @@ gpio0: gpio@0209c000 { /* GPIO1 */
#interrupt-cells = <1>;
};
gpio1: gpio@020a0000 { /* GPIO2 */
gpio2: gpio@020a0000 {
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
reg = <0x020a0000 0x4000>;
interrupts = <0 68 0x04 0 69 0x04>;
@ -267,7 +267,7 @@ gpio1: gpio@020a0000 { /* GPIO2 */
#interrupt-cells = <1>;
};
gpio2: gpio@020a4000 { /* GPIO3 */
gpio3: gpio@020a4000 {
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
reg = <0x020a4000 0x4000>;
interrupts = <0 70 0x04 0 71 0x04>;
@ -277,7 +277,7 @@ gpio2: gpio@020a4000 { /* GPIO3 */
#interrupt-cells = <1>;
};
gpio3: gpio@020a8000 { /* GPIO4 */
gpio4: gpio@020a8000 {
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
reg = <0x020a8000 0x4000>;
interrupts = <0 72 0x04 0 73 0x04>;
@ -287,7 +287,7 @@ gpio3: gpio@020a8000 { /* GPIO4 */
#interrupt-cells = <1>;
};
gpio4: gpio@020ac000 { /* GPIO5 */
gpio5: gpio@020ac000 {
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
reg = <0x020ac000 0x4000>;
interrupts = <0 74 0x04 0 75 0x04>;
@ -297,7 +297,7 @@ gpio4: gpio@020ac000 { /* GPIO5 */
#interrupt-cells = <1>;
};
gpio5: gpio@020b0000 { /* GPIO6 */
gpio6: gpio@020b0000 {
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
reg = <0x020b0000 0x4000>;
interrupts = <0 76 0x04 0 77 0x04>;
@ -307,7 +307,7 @@ gpio5: gpio@020b0000 { /* GPIO6 */
#interrupt-cells = <1>;
};
gpio6: gpio@020b4000 { /* GPIO7 */
gpio7: gpio@020b4000 {
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
reg = <0x020b4000 0x4000>;
interrupts = <0 78 0x04 0 79 0x04>;
@ -543,28 +543,28 @@ vdoa@021e4000 {
interrupts = <0 18 0x04>;
};
uart1: uart@021e8000 { /* UART2 */
uart2: uart@021e8000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021e8000 0x4000>;
interrupts = <0 27 0x04>;
status = "disabled";
};
uart2: uart@021ec000 { /* UART3 */
uart3: uart@021ec000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021ec000 0x4000>;
interrupts = <0 28 0x04>;
status = "disabled";
};
uart3: uart@021f0000 { /* UART4 */
uart4: uart@021f0000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f0000 0x4000>;
interrupts = <0 29 0x04>;
status = "disabled";
};
uart4: uart@021f4000 { /* UART5 */
uart5: uart@021f4000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f4000 0x4000>;
interrupts = <0 30 0x04>;

1
arch/arm/configs/imx_v4_v5_defconfig
View File

@ -68,7 +68,6 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
# CONFIG_MTD_CFI_I2 is not set
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y

1
arch/arm/mach-imx/Kconfig
View File

@ -98,6 +98,7 @@ config MACH_SCB9328
config MACH_APF9328
bool "APF9328"
select SOC_IMX1
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
help
Say Yes here if you are using the Armadeus APF9328 development board

3
arch/arm/mach-imx/Makefile.boot
View File

@ -25,3 +25,6 @@ initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000
zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000
params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
imx6q-sabrelite.dtb

10
arch/arm/mach-imx/mach-apf9328.c
View File

@ -18,6 +18,7 @@
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/dm9000.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -41,6 +42,9 @@ static const int apf9328_pins[] __initconst = {
PB29_PF_UART2_RTS,
PB30_PF_UART2_TXD,
PB31_PF_UART2_RXD,
/* I2C */
PA15_PF_I2C_SDA,
PA16_PF_I2C_SCL,
};
/*
@ -103,6 +107,10 @@ static const struct imxuart_platform_data uart1_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static const struct imxi2c_platform_data apf9328_i2c_data __initconst = {
.bitrate = 100000,
};
static struct platform_device *devices[] __initdata = {
&apf9328_flash_device,
&dm9000x_device,
@ -119,6 +127,8 @@ static void __init apf9328_init(void)
imx1_add_imx_uart0(NULL);
imx1_add_imx_uart1(&uart1_pdata);
imx1_add_imx_i2c(&apf9328_i2c_data);
platform_add_devices(devices, ARRAY_SIZE(devices));
}

24
arch/arm/mach-imx/mach-imx6q.c
View File

@ -19,6 +19,8 @@
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
#include <linux/micrel_phy.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
@ -56,8 +58,27 @@ void imx6q_restart(char mode, const char *cmd)
soft_restart(0);
}
/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
static int ksz9021rn_phy_fixup(struct phy_device *phydev)
{
/* min rx data delay */
phy_write(phydev, 0x0b, 0x8105);
phy_write(phydev, 0x0c, 0x0000);
/* max rx/tx clock delay, min rx/tx control delay */
phy_write(phydev, 0x0b, 0x8104);
phy_write(phydev, 0x0c, 0xf0f0);
phy_write(phydev, 0x0b, 0x104);
return 0;
}
static void __init imx6q_init_machine(void)
{
if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
ksz9021rn_phy_fixup);
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
imx6q_pm_init();
@ -105,7 +126,8 @@ static struct sys_timer imx6q_timer = {
};
static const char *imx6q_dt_compat[] __initdata = {
"fsl,imx6q-sabreauto",
"fsl,imx6q-arm2",
"fsl,imx6q-sabrelite",
NULL,
};

2
arch/arm/mach-imx/mach-mx31_3ds.c
View File

@ -492,7 +492,7 @@ static struct mc13xxx_platform_data mc13783_pdata = {
.regulators = mx31_3ds_regulators,
.num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
},
.flags = MC13XXX_USE_TOUCHSCREEN,
.flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC,
};
/* SPI */

5
arch/arm/mach-omap2/Kconfig
View File

@ -324,6 +324,11 @@ config MACH_TI8168EVM
depends on SOC_OMAPTI81XX
default y
config MACH_TI8148EVM
bool "TI8148 Evaluation Module"
depends on SOC_OMAPTI81XX
default y
config MACH_OMAP_4430SDP
bool "OMAP 4430 SDP board"
default y

1
arch/arm/mach-omap2/Makefile
View File

@ -232,6 +232,7 @@ obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o
obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o
obj-$(CONFIG_MACH_TI8148EVM) += board-ti8168evm.o
# Platform specific device init code

6
arch/arm/mach-omap2/board-4430sdp.c
View File

@ -372,11 +372,17 @@ static struct platform_device sdp4430_vbat = {
},
};
static struct platform_device sdp4430_dmic_codec = {
.name = "dmic-codec",
.id = -1,
};
static struct platform_device *sdp4430_devices[] __initdata = {
&sdp4430_gpio_keys_device,
&sdp4430_leds_gpio,
&sdp4430_leds_pwm,
&sdp4430_vbat,
&sdp4430_dmic_codec,
};
static struct omap_musb_board_data musb_board_data = {

82
arch/arm/mach-omap2/board-cm-t35.c
View File

@ -53,7 +53,8 @@
#include "hsmmc.h"
#include "common-board-devices.h"
#define CM_T35_GPIO_PENDOWN 57
#define CM_T35_GPIO_PENDOWN 57
#define SB_T35_USB_HUB_RESET_GPIO 167
#define CM_T35_SMSC911X_CS 5
#define CM_T35_SMSC911X_GPIO 163
@ -339,8 +340,10 @@ static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply cm_t35_vdvi_supply[] = {
REGULATOR_SUPPLY("vdvi", "omapdss"),
static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
REGULATOR_SUPPLY("vcc", "spi1.0"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@ -373,6 +376,19 @@ static struct regulator_init_data cm_t35_vsim = {
.consumer_supplies = cm_t35_vsim_supply,
};
static struct regulator_init_data cm_t35_vio = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE,
},
.num_consumer_supplies = ARRAY_SIZE(cm_t35_vio_supplies),
.consumer_supplies = cm_t35_vio_supplies,
};
static uint32_t cm_t35_keymap[] = {
KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT),
KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN),
@ -421,6 +437,23 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
.reset_gpio_port[2] = -EINVAL
};
static void cm_t35_init_usbh(void)
{
int err;
err = gpio_request_one(SB_T35_USB_HUB_RESET_GPIO,
GPIOF_OUT_INIT_LOW, "usb hub rst");
if (err) {
pr_err("SB-T35: usb hub rst gpio request failed: %d\n", err);
} else {
udelay(10);
gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
msleep(1);
}
usbhs_init(&usbhs_bdata);
}
static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
unsigned ngpio)
{
@ -456,17 +489,14 @@ static struct twl4030_platform_data cm_t35_twldata = {
.gpio = &cm_t35_gpio_data,
.vmmc1 = &cm_t35_vmmc1,
.vsim = &cm_t35_vsim,
.vio = &cm_t35_vio,
};
static void __init cm_t35_init_i2c(void)
{
omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
cm_t35_twldata.vpll2->constraints.name = "VDVI";
cm_t35_twldata.vpll2->num_consumer_supplies =
ARRAY_SIZE(cm_t35_vdvi_supply);
cm_t35_twldata.vpll2->consumer_supplies = cm_t35_vdvi_supply;
TWL_COMMON_REGULATOR_VDAC |
TWL_COMMON_PDATA_AUDIO);
omap3_pmic_init("tps65930", &cm_t35_twldata);
}
@ -570,24 +600,28 @@ static void __init cm_t3x_common_dss_mux_init(int mux_mode)
static void __init cm_t35_init_mux(void)
{
omap_mux_init_signal("gpio_70", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpio_71", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpio_72", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpio_73", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpio_74", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpio_75", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
cm_t3x_common_dss_mux_init(OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
int mux_mode = OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT;
omap_mux_init_signal("dss_data0.dss_data0", mux_mode);
omap_mux_init_signal("dss_data1.dss_data1", mux_mode);
omap_mux_init_signal("dss_data2.dss_data2", mux_mode);
omap_mux_init_signal("dss_data3.dss_data3", mux_mode);
omap_mux_init_signal("dss_data4.dss_data4", mux_mode);
omap_mux_init_signal("dss_data5.dss_data5", mux_mode);
cm_t3x_common_dss_mux_init(mux_mode);
}
static void __init cm_t3730_init_mux(void)
{
omap_mux_init_signal("sys_boot0", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
omap_mux_init_signal("sys_boot1", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
omap_mux_init_signal("sys_boot3", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
omap_mux_init_signal("sys_boot4", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
omap_mux_init_signal("sys_boot5", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
omap_mux_init_signal("sys_boot6", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
cm_t3x_common_dss_mux_init(OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
int mux_mode = OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT;
omap_mux_init_signal("sys_boot0", mux_mode);
omap_mux_init_signal("sys_boot1", mux_mode);
omap_mux_init_signal("sys_boot3", mux_mode);
omap_mux_init_signal("sys_boot4", mux_mode);
omap_mux_init_signal("sys_boot5", mux_mode);
omap_mux_init_signal("sys_boot6", mux_mode);
cm_t3x_common_dss_mux_init(mux_mode);
}
#else
static inline void cm_t35_init_mux(void) {}
@ -612,7 +646,7 @@ static void __init cm_t3x_common_init(void)
cm_t35_init_display();
usb_musb_init(NULL);
usbhs_init(&usbhs_bdata);
cm_t35_init_usbh();
}
static void __init cm_t35_init(void)

46
arch/arm/mach-omap2/board-rx51-peripherals.c
View File

@ -15,6 +15,7 @@
#include <linux/input/matrix_keypad.h>
#include <linux/spi/spi.h>
#include <linux/wl12xx.h>
#include <linux/spi/tsc2005.h>
#include <linux/i2c.h>
#include <linux/i2c/twl.h>
#include <linux/clk.h>
@ -58,6 +59,9 @@
#define RX51_USB_TRANSCEIVER_RST_GPIO 67
#define RX51_TSC2005_RESET_GPIO 104
#define RX51_TSC2005_IRQ_GPIO 100
/* list all spi devices here */
enum {
RX51_SPI_WL1251,
@ -66,6 +70,7 @@ enum {
};
static struct wl12xx_platform_data wl1251_pdata;
static struct tsc2005_platform_data tsc2005_pdata;
#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
@ -167,10 +172,10 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
.modalias = "tsc2005",
.bus_num = 1,
.chip_select = 0,
/* .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),*/
.irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),
.max_speed_hz = 6000000,
.controller_data = &tsc2005_mcspi_config,
/* .platform_data = &tsc2005_config,*/
.platform_data = &tsc2005_pdata,
},
};
@ -1086,6 +1091,42 @@ static void __init rx51_init_wl1251(void)
*/
}
static struct tsc2005_platform_data tsc2005_pdata = {
.ts_pressure_max = 2048,
.ts_pressure_fudge = 2,
.ts_x_max = 4096,
.ts_x_fudge = 4,
.ts_y_max = 4096,
.ts_y_fudge = 7,
.ts_x_plate_ohm = 280,
.esd_timeout_ms = 8000,
};
static void rx51_tsc2005_set_reset(bool enable)
{
gpio_set_value(RX51_TSC2005_RESET_GPIO, enable);
}
static void __init rx51_init_tsc2005(void)
{
int r;
r = gpio_request_one(RX51_TSC2005_IRQ_GPIO, GPIOF_IN, "tsc2005 IRQ");
if (r < 0) {
printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 IRQ");
rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq = 0;
}
r = gpio_request_one(RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH,
"tsc2005 reset");
if (r >= 0) {
tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
} else {
printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 reset");
tsc2005_pdata.esd_timeout_ms = 0;
}
}
void __init rx51_peripherals_init(void)
{
rx51_i2c_init();
@ -1094,6 +1135,7 @@ void __init rx51_peripherals_init(void)
board_smc91x_init();
rx51_add_gpio_keys();
rx51_init_wl1251();
rx51_init_tsc2005();
rx51_init_si4713();
spi_register_board_info(rx51_peripherals_spi_board_info,
ARRAY_SIZE(rx51_peripherals_spi_board_info));

32
arch/arm/mach-omap2/board-ti8168evm.c
View File

@ -1,5 +1,5 @@
/*
* Code for TI8168 EVM.
* Code for TI8168/TI8148 EVM.
*
* Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
*
@ -23,16 +23,25 @@
#include <plat/irqs.h>
#include <plat/board.h>
#include "common.h"
#include <plat/usb.h>
static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
static struct omap_musb_board_data musb_board_data = {
.set_phy_power = ti81xx_musb_phy_power,
.interface_type = MUSB_INTERFACE_ULPI,
.mode = MUSB_OTG,
.power = 500,
};
static void __init ti8168_evm_init(void)
static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = {
};
static void __init ti81xx_evm_init(void)
{
omap_serial_init();
omap_sdrc_init(NULL, NULL);
omap_board_config = ti8168_evm_config;
omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
omap_board_config = ti81xx_evm_config;
omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config);
usb_musb_init(&musb_board_data);
}
MACHINE_START(TI8168EVM, "ti8168evm")
@ -42,6 +51,17 @@ MACHINE_START(TI8168EVM, "ti8168evm")
.init_early = ti81xx_init_early,
.init_irq = ti81xx_init_irq,
.timer = &omap3_timer,
.init_machine = ti8168_evm_init,
.init_machine = ti81xx_evm_init,
.restart = omap_prcm_restart,
MACHINE_END
MACHINE_START(TI8148EVM, "ti8148evm")
/* Maintainer: Texas Instruments */
.atag_offset = 0x100,
.map_io = ti81xx_map_io,
.init_early = ti81xx_init_early,
.init_irq = ti81xx_init_irq,
.timer = &omap3_timer,
.init_machine = ti81xx_evm_init,
.restart = omap_prcm_restart,
MACHINE_END

22
arch/arm/mach-omap2/devices.c
View File

@ -336,6 +336,27 @@ static void omap_init_mcpdm(void)
static inline void omap_init_mcpdm(void) {}
#endif
#if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
static void omap_init_dmic(void)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
oh = omap_hwmod_lookup("dmic");
if (!oh) {
printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
return;
}
pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
}
#else
static inline void omap_init_dmic(void) {}
#endif
#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
#include <plat/mcspi.h>
@ -681,6 +702,7 @@ static int __init omap2_init_devices(void)
*/
omap_init_audio();
omap_init_mcpdm();
omap_init_dmic();
omap_init_camera();
omap_init_mbox();
omap_init_mcspi();

35
arch/arm/mach-omap2/omap_phy_internal.c
View File

@ -260,3 +260,38 @@ void am35x_set_mode(u8 musb_mode)
omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
}
void ti81xx_musb_phy_power(u8 on)
{
void __iomem *scm_base = NULL;
u32 usbphycfg;
scm_base = ioremap(TI81XX_SCM_BASE, SZ_2K);
if (!scm_base) {
pr_err("system control module ioremap failed\n");
return;
}
usbphycfg = __raw_readl(scm_base + USBCTRL0);
if (on) {
if (cpu_is_ti816x()) {
usbphycfg |= TI816X_USBPHY0_NORMAL_MODE;
usbphycfg &= ~TI816X_USBPHY_REFCLK_OSC;
} else if (cpu_is_ti814x()) {
usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN
| USBPHY_DPINPUT | USBPHY_DMINPUT);
usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN
| USBPHY_DPOPBUFCTL | USBPHY_DMOPBUFCTL);
}
} else {
if (cpu_is_ti816x())
usbphycfg &= ~TI816X_USBPHY0_NORMAL_MODE;
else if (cpu_is_ti814x())
usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
}
__raw_writel(usbphycfg, scm_base + USBCTRL0);
iounmap(scm_base);
}

25
arch/arm/mach-omap2/sdram-nokia.c
View File

@ -1,7 +1,7 @@
/*
* SDRC register values for Nokia boards
*
* Copyright (C) 2008, 2010 Nokia Corporation
* Copyright (C) 2008, 2010-2011 Nokia Corporation
*
* Lauri Leukkunen <lauri.leukkunen@nokia.com>
*
@ -107,14 +107,37 @@ static const struct sdram_timings nokia_195dot2mhz_timings[] = {
},
};
static const struct sdram_timings nokia_200mhz_timings[] = {
{
.casl = 3,
.tDAL = 30000,
.tDPL = 15000,
.tRRD = 10000,
.tRCD = 20000,
.tRP = 15000,
.tRAS = 40000,
.tRC = 55000,
.tRFC = 140000,
.tXSR = 200000,
.tREF = 7800,
.tXP = 2,
.tCKE = 4,
.tWTR = 2
},
};
static const struct {
long rate;
struct sdram_timings const *data;
} nokia_timings[] = {
{ 83000000, nokia_166mhz_timings },
{ 97600000, nokia_97dot6mhz_timings },
{ 100000000, nokia_200mhz_timings },
{ 166000000, nokia_166mhz_timings },
{ 195200000, nokia_195dot2mhz_timings },
{ 200000000, nokia_200mhz_timings },
};
static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1];

3
arch/arm/mach-omap2/usb-musb.c
View File

@ -93,6 +93,9 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
if (cpu_is_omap3517() || cpu_is_omap3505()) {
oh_name = "am35x_otg_hs";
name = "musb-am35x";
} else if (cpu_is_ti81xx()) {
oh_name = "usb_otg_hs";
name = "musb-ti81xx";
} else {
oh_name = "usb_otg_hs";
name = "musb-omap2430";

29
arch/arm/mach-pxa/mioa701.c
View File

@ -53,6 +53,7 @@
#include <mach/pxa27x-udc.h>
#include <mach/camera.h>
#include <mach/audio.h>
#include <mach/smemc.h>
#include <media/soc_camera.h>
#include <mach/mioa701.h>
@ -390,24 +391,19 @@ static struct pxamci_platform_data mioa701_mci_info = {
};
/* FlashRAM */
static struct resource strataflash_resource = {
static struct resource docg3_resource = {
.start = PXA_CS0_PHYS,
.end = PXA_CS0_PHYS + SZ_64M - 1,
.end = PXA_CS0_PHYS + SZ_8K - 1,
.flags = IORESOURCE_MEM,
};
static struct physmap_flash_data strataflash_data = {
.width = 2,
/* .set_vpp = mioa701_set_vpp, */
};
static struct platform_device strataflash = {
.name = "physmap-flash",
static struct platform_device docg3 = {
.name = "docg3",
.id = -1,
.resource = &strataflash_resource,
.resource = &docg3_resource,
.num_resources = 1,
.dev = {
.platform_data = &strataflash_data,
.platform_data = NULL,
},
};
@ -685,7 +681,7 @@ static struct platform_device *devices[] __initdata = {
&pxa2xx_pcm,
&mioa701_sound,
&power_dev,
&strataflash,
&docg3,
&gpio_vbus,
&mioa701_camera,
&mioa701_board,
@ -720,6 +716,15 @@ static void __init mioa701_machine_init(void)
RTTR = 32768 - 1; /* Reset crazy WinCE value */
UP2OCR = UP2OCR_HXOE;
/*
* Set up the flash memory : DiskOnChip G3 on first static memory bank
*/
__raw_writel(0x7ff02dd8, MSC0);
__raw_writel(0x0001c391, MCMEM0);
__raw_writel(0x0001c391, MCATT0);
__raw_writel(0x0001c391, MCIO0);
pxa2xx_mfp_config(ARRAY_AND_SIZE(mioa701_pin_config));
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);

18
arch/arm/mach-s3c2440/mach-mini2440.c
View File

@ -169,6 +169,24 @@ static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
.lcdcon5 = (S3C2410_LCDCON5_FRM565 |
S3C2410_LCDCON5_HWSWP),
},
/* mini2440 + 3.5" TFT (LCD-W35i, LQ035Q1DG06 type) + touchscreen*/
[3] = {
_LCD_DECLARE(
/* clock */
7,
/* xres, margin_right, margin_left, hsync */
320, 68, 66, 4,
/* yres, margin_top, margin_bottom, vsync */
240, 4, 4, 9,
/* refresh rate */
60),
.lcdcon5 = (S3C2410_LCDCON5_FRM565 |
S3C2410_LCDCON5_INVVDEN |
S3C2410_LCDCON5_INVVFRAME |
S3C2410_LCDCON5_INVVLINE |
S3C2410_LCDCON5_INVVCLK |
S3C2410_LCDCON5_HWSWP),
},
};
/* todo - put into gpio header */

6
arch/arm/mach-s3c64xx/Kconfig
View File

@ -194,7 +194,7 @@ config SMDK6410_WM1190_EV1
depends on MACH_SMDK6410
select REGULATOR
select REGULATOR_WM8350
select S3C24XX_GPIO_EXTRA64
select SAMSUNG_GPIO_EXTRA64
select MFD_WM8350_I2C
select MFD_WM8350_CONFIG_MODE_0
select MFD_WM8350_CONFIG_MODE_3
@ -212,7 +212,7 @@ config SMDK6410_WM1192_EV1
depends on MACH_SMDK6410
select REGULATOR
select REGULATOR_WM831X
select S3C24XX_GPIO_EXTRA64
select SAMSUNG_GPIO_EXTRA64
select MFD_WM831X
select MFD_WM831X_I2C
help
@ -294,7 +294,7 @@ config MACH_WLF_CRAGG_6410
select S3C_DEV_WDT
select S3C_DEV_RTC
select S3C64XX_DEV_SPI0
select S3C24XX_GPIO_EXTRA128
select SAMSUNG_GPIO_EXTRA128
select I2C
help
Machine support for the Wolfson Cragganmore S3C6410 variant.

6
arch/arm/mach-s3c64xx/include/mach/crag6410.h
View File

@ -15,9 +15,11 @@
#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START
#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
#define CODEC_IRQ_BASE (IRQ_BOARD_START + 128)
#define PCA935X_GPIO_BASE GPIO_BOARD_START
#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16)
#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 32)
#define BANFF_PMIC_GPIO_BASE (GPIO_BOARD_START + 64)
#endif

2
arch/arm/mach-s3c64xx/include/mach/gpio.h
View File

@ -88,6 +88,6 @@ enum s3c_gpio_number {
/* define the number of gpios we need to the one after the GPQ() range */
#define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
#define BOARD_NR_GPIOS 16
#define BOARD_NR_GPIOS (16 + CONFIG_SAMSUNG_GPIO_EXTRA)
#define ARCH_NR_GPIOS (GPIO_BOARD_START + BOARD_NR_GPIOS)

2
arch/arm/mach-s3c64xx/include/mach/irqs.h
View File

@ -169,7 +169,7 @@
#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
#ifdef CONFIG_MACH_WLF_CRAGG_6410
#define IRQ_BOARD_NR 128
#define IRQ_BOARD_NR 160
#elif defined(CONFIG_SMDK6410_WM1190_EV1)
#define IRQ_BOARD_NR 64
#elif defined(CONFIG_SMDK6410_WM1192_EV1)

56
arch/arm/mach-s3c64xx/mach-crag6410-module.c
View File

@ -14,13 +14,43 @@
#include <linux/mfd/wm831x/irq.h>
#include <linux/mfd/wm831x/gpio.h>
#include <linux/mfd/wm8994/pdata.h>
#include <sound/wm5100.h>
#include <sound/wm8996.h>
#include <sound/wm8962.h>
#include <sound/wm9081.h>
#include <mach/crag6410.h>
static struct wm5100_pdata wm5100_pdata = {
.ldo_ena = S3C64XX_GPN(7),
.irq_flags = IRQF_TRIGGER_HIGH,
.gpio_base = CODEC_GPIO_BASE,
.in_mode = {
WM5100_IN_DIFF,
WM5100_IN_DIFF,
WM5100_IN_DIFF,
WM5100_IN_SE,
},
.hp_pol = CODEC_GPIO_BASE + 3,
.jack_modes = {
{ WM5100_MICDET_MICBIAS3, 0, 0 },
{ WM5100_MICDET_MICBIAS2, 1, 1 },
},
.gpio_defaults = {
0,
0,
0,
0,
0x2, /* IRQ: CMOS output */
0x3, /* CLKOUT: CMOS output */
},
};
static struct wm8996_retune_mobile_config wm8996_retune[] = {
{
.name = "Sub LPF",
@ -72,7 +102,6 @@ static struct wm8962_pdata wm8962_pdata __initdata = {
0x8000 | WM8962_GPIO_FN_DMICDAT,
WM8962_GPIO_FN_IRQ, /* Open drain mode */
},
.irq_active_low = true,
};
static struct wm9081_pdata wm9081_pdata __initdata = {
@ -91,6 +120,7 @@ static const struct i2c_board_info wm1254_devs[] = {
static const struct i2c_board_info wm1255_devs[] = {
{ I2C_BOARD_INFO("wm5100", 0x1a),
.platform_data = &wm5100_pdata,
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
},
{ I2C_BOARD_INFO("wm9081", 0x6c),
@ -104,6 +134,24 @@ static const struct i2c_board_info wm1259_devs[] = {
},
};
static struct wm8994_pdata wm8994_pdata = {
.gpio_base = CODEC_GPIO_BASE,
.gpio_defaults = {
0x3, /* IRQ out, active high, CMOS */
},
.irq_base = CODEC_IRQ_BASE,
.ldo = {
{ .supply = "WALLVDD" },
{ .supply = "WALLVDD" },
},
};
static const struct i2c_board_info wm1277_devs[] = {
{ I2C_BOARD_INFO("wm8958", 0x1a), /* WM8958 is the superset */
.platform_data = &wm8994_pdata,
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
},
};
static __devinitdata const struct {
u8 id;
@ -125,6 +173,8 @@ static __devinitdata const struct {
{ .id = 0x3b, .name = "1255-EV1 Kilchoman",
.i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
{ .id = 0x3c, .name = "1273-EV1 Longmorn" },
{ .id = 0x3d, .name = "1277-EV1 Littlemill",
.i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) },
};
static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
@ -154,8 +204,8 @@ static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
"Failed to register dev: %d\n", ret);
}
} else {
dev_warn(&i2c->dev, "Unknown module ID %d revision %d\n",
id, rev);
dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n",
id, rev + 1);
}
return 0;

39
arch/arm/mach-s3c64xx/mach-crag6410.c
View File

@ -37,6 +37,8 @@
#include <linux/mfd/wm831x/irq.h>
#include <linux/mfd/wm831x/gpio.h>
#include <sound/wm1250-ev1.h>
#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@ -289,6 +291,11 @@ static struct platform_device speyside_wm8962_device = {
.id = -1,
};
static struct platform_device littlemill_device = {
.name = "littlemill",
.id = -1,
};
static struct regulator_consumer_supply wallvdd_consumers[] = {
REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
@ -341,6 +348,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
&crag6410_backlight_device,
&speyside_device,
&speyside_wm8962_device,
&littlemill_device,
&lowland_device,
&wallvdd_device,
};
@ -374,6 +382,10 @@ static struct regulator_init_data vddarm __initdata = {
.driver_data = &vddarm_pdata,
};
static struct regulator_consumer_supply vddint_consumers[] __initdata = {
REGULATOR_SUPPLY("vddint", NULL),
};
static struct regulator_init_data vddint __initdata = {
.constraints = {
.name = "VDDINT",
@ -382,6 +394,9 @@ static struct regulator_init_data vddint __initdata = {
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(vddint_consumers),
.consumer_supplies = vddint_consumers,
.supply_regulator = "WALLVDD",
};
static struct regulator_init_data vddmem __initdata = {
@ -502,7 +517,8 @@ static struct wm831x_touch_pdata touch_pdata __initdata = {
static struct wm831x_pdata crag_pmic_pdata __initdata = {
.wm831x_num = 1,
.irq_base = BANFF_PMIC_IRQ_BASE,
.gpio_base = GPIO_BOARD_START + 8,
.gpio_base = BANFF_PMIC_GPIO_BASE,
.soft_shutdown = true,
.backup = &banff_backup_pdata,
@ -607,6 +623,7 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
.wm831x_num = 2,
.irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
.gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
.soft_shutdown = true,
.gpio_defaults = {
/* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
@ -624,6 +641,16 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
.disable_touch = true,
};
static struct wm1250_ev1_pdata wm1250_ev1_pdata = {
.gpios = {
[WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12),
[WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12),
[WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13),
[WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14),
[WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8),
},
};
static struct i2c_board_info i2c_devs1[] __initdata = {
{ I2C_BOARD_INFO("wm8311", 0x34),
.irq = S3C_EINT(0),
@ -633,7 +660,13 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
{ I2C_BOARD_INFO("wlf-gf-module", 0x25) },
{ I2C_BOARD_INFO("wlf-gf-module", 0x26) },
{ I2C_BOARD_INFO("wm1250-ev1", 0x27) },
{ I2C_BOARD_INFO("wm1250-ev1", 0x27),
.platform_data = &wm1250_ev1_pdata },
};
static struct s3c2410_platform_i2c i2c1_pdata = {
.frequency = 400000,
.bus_num = 1,
};
static void __init crag6410_map_io(void)
@ -694,7 +727,7 @@ static void __init crag6410_machine_init(void)
s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
s3c_i2c0_set_platdata(&i2c0_pdata);
s3c_i2c1_set_platdata(NULL);
s3c_i2c1_set_platdata(&i2c1_pdata);
s3c_fb_set_platdata(&crag6410_lcd_pdata);
i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));

13
arch/arm/mach-s3c64xx/pm.c
View File

@ -346,10 +346,23 @@ int __init s3c64xx_pm_init(void)
static __init int s3c64xx_pm_initcall(void)
{
u32 val;
pm_cpu_prep = s3c64xx_pm_prepare;
pm_cpu_sleep = s3c64xx_cpu_suspend;
pm_uart_udivslot = 1;
/*
* Unconditionally disable power domains that contain only
* blocks which have no mainline driver support.
*/
val = __raw_readl(S3C64XX_NORMAL_CFG);
val &= ~(S3C64XX_NORMALCFG_DOMAIN_G_ON |
S3C64XX_NORMALCFG_DOMAIN_V_ON |
S3C64XX_NORMALCFG_DOMAIN_I_ON |
S3C64XX_NORMALCFG_DOMAIN_P_ON);
__raw_writel(val, S3C64XX_NORMAL_CFG);
#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");

1
arch/arm/mach-tegra/Makefile
View File

@ -1,3 +1,4 @@
obj-y += board-pinmux.o
obj-y += common.o
obj-y += devices.o
obj-y += io.o

16
arch/arm/mach-tegra/board-dt-tegra20.c
View File

@ -54,6 +54,8 @@ void trimslice_pinmux_init(void);
void ventana_pinmux_init(void);
struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
@ -110,13 +112,6 @@ static void __init tegra_dt_init(void)
tegra_clk_init_from_table(tegra_dt_clk_init_table);
/*
* Finished with the static registrations now; fill in the missing
* devices
*/
of_platform_populate(NULL, tegra_dt_match_table,
tegra20_auxdata_lookup, NULL);
for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
if (of_machine_is_compatible(pinmux_configs[i].machine)) {
pinmux_configs[i].init();
@ -126,6 +121,13 @@ static void __init tegra_dt_init(void)
WARN(i == ARRAY_SIZE(pinmux_configs),
"Unknown platform! Pinmuxing not initialized\n");
/*
* Finished with the static registrations now; fill in the missing
* devices
*/
of_platform_populate(NULL, tegra_dt_match_table,
tegra20_auxdata_lookup, NULL);
}
static const char *tegra20_dt_board_compat[] = {

10
arch/arm/mach-tegra/board-harmony-pcie.c
View File

@ -22,8 +22,6 @@
#include <asm/mach-types.h>
#include <mach/pinmux.h>
#include <mach/pinmux-tegra20.h>
#include "board.h"
#include "board-harmony.h"
@ -49,10 +47,6 @@ static int __init harmony_pcie_init(void)
regulator_enable(regulator);
tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_NORMAL);
tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_NORMAL);
tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_NORMAL);
err = tegra_pcie_init(true, true);
if (err)
goto err_pcie;
@ -60,10 +54,6 @@ static int __init harmony_pcie_init(void)
return 0;
err_pcie:
tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_TRISTATE);
tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_TRISTATE);
tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_TRISTATE);
regulator_disable(regulator);
regulator_put(regulator);
err_reg:

22
arch/arm/mach-tegra/board-harmony-pinmux.c
View File

@ -23,7 +23,7 @@
#include "gpio-names.h"
#include "board-harmony.h"
#include "devices.h"
#include "board-pinmux.h"
static struct tegra_pingroup_config harmony_pinmux[] = {
{TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
@ -144,11 +144,6 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
{TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
};
static struct platform_device *pinmux_devices[] = {
&tegra_gpio_device,
&tegra_pinmux_device,
};
static struct tegra_gpio_table gpio_table[] = {
{ .gpio = TEGRA_GPIO_SD2_CD, .enable = true },
{ .gpio = TEGRA_GPIO_SD2_WP, .enable = true },
@ -162,13 +157,14 @@ static struct tegra_gpio_table gpio_table[] = {
{ .gpio = TEGRA_GPIO_EXT_MIC_EN, .enable = true },
};
static struct tegra_board_pinmux_conf conf = {
.pgs = harmony_pinmux,
.pg_count = ARRAY_SIZE(harmony_pinmux),
.gpios = gpio_table,
.gpio_count = ARRAY_SIZE(gpio_table),
};
void harmony_pinmux_init(void)
{
if (!of_machine_is_compatible("nvidia,tegra20"))
platform_add_devices(pinmux_devices,
ARRAY_SIZE(pinmux_devices));
tegra_pinmux_config_table(harmony_pinmux, ARRAY_SIZE(harmony_pinmux));
tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
tegra_board_pinmux_init(&conf, NULL);
}

24
arch/arm/mach-tegra/board-paz00-pinmux.c
View File

@ -23,7 +23,7 @@
#include "gpio-names.h"
#include "board-paz00.h"
#include "devices.h"
#include "board-pinmux.h"
static struct tegra_pingroup_config paz00_pinmux[] = {
{TEGRA_PINGROUP_ATA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
@ -31,7 +31,7 @@ static struct tegra_pingroup_config paz00_pinmux[] = {
{TEGRA_PINGROUP_ATC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_CSUS, TEGRA_MUX_PLLC_OUT1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
@ -144,11 +144,6 @@ static struct tegra_pingroup_config paz00_pinmux[] = {
{TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
};
static struct platform_device *pinmux_devices[] = {
&tegra_gpio_device,
&tegra_pinmux_device,
};
static struct tegra_gpio_table gpio_table[] = {
{ .gpio = TEGRA_GPIO_SD1_CD, .enable = true },
{ .gpio = TEGRA_GPIO_SD1_WP, .enable = true },
@ -159,13 +154,14 @@ static struct tegra_gpio_table gpio_table[] = {
{ .gpio = TEGRA_WIFI_LED, .enable = true },
};
static struct tegra_board_pinmux_conf conf = {
.pgs = paz00_pinmux,
.pg_count = ARRAY_SIZE(paz00_pinmux),
.gpios = gpio_table,
.gpio_count = ARRAY_SIZE(gpio_table),
};
void paz00_pinmux_init(void)
{
if (!of_machine_is_compatible("nvidia,tegra20"))
platform_add_devices(pinmux_devices,
ARRAY_SIZE(pinmux_devices));
tegra_pinmux_config_table(paz00_pinmux, ARRAY_SIZE(paz00_pinmux));
tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
tegra_board_pinmux_init(&conf, NULL);
}

27
arch/arm/mach-tegra/board-paz00.c
View File

@ -23,8 +23,10 @@
#include <linux/serial_8250.h>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/gpio_keys.h>
#include <linux/pda_power.h>
#include <linux/io.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/rfkill-gpio.h>
@ -115,12 +117,37 @@ static struct platform_device leds_gpio = {
},
};
static struct gpio_keys_button paz00_gpio_keys_buttons[] = {
{
.code = KEY_POWER,
.gpio = TEGRA_GPIO_POWERKEY,
.active_low = 1,
.desc = "Power",
.type = EV_KEY,
.wakeup = 1,
},
};
static struct gpio_keys_platform_data paz00_gpio_keys = {
.buttons = paz00_gpio_keys_buttons,
.nbuttons = ARRAY_SIZE(paz00_gpio_keys_buttons),
};
static struct platform_device gpio_keys_device = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &paz00_gpio_keys,
},
};
static struct platform_device *paz00_devices[] __initdata = {
&debug_uart,
&tegra_sdhci_device4,
&tegra_sdhci_device1,
&wifi_rfkill_device,
&leds_gpio,
&gpio_keys_device,
};
static void paz00_i2c_init(void)

3
arch/arm/mach-tegra/board-paz00.h
View File

@ -32,6 +32,9 @@
#define TEGRA_WIFI_RST TEGRA_GPIO_PD1
#define TEGRA_WIFI_LED TEGRA_GPIO_PD0
/* WakeUp */
#define TEGRA_GPIO_POWERKEY TEGRA_GPIO_PJ7
void paz00_pinmux_init(void);
#endif

104
arch/arm/mach-tegra/board-pinmux.c Normal file
View File

@ -0,0 +1,104 @@
/*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/notifier.h>
#include <linux/of.h>
#include <linux/string.h>
#include <mach/gpio-tegra.h>
#include <mach/pinmux.h>
#include "board-pinmux.h"
#include "devices.h"
struct tegra_board_pinmux_conf *confs[2];
static void tegra_board_pinmux_setup_gpios(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(confs); i++) {
if (!confs[i])
continue;
tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count);
}
}
static void tegra_board_pinmux_setup_pinmux(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(confs); i++) {
if (!confs[i])
continue;
tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count);
if (confs[i]->drives)
tegra_drive_pinmux_config_table(confs[i]->drives,
confs[i]->drive_count);
}
}
static int tegra_board_pinmux_bus_notify(struct notifier_block *nb,
unsigned long event, void *vdev)
{
static bool had_gpio;
static bool had_pinmux;
struct device *dev = vdev;
const char *devname;
if (event != BUS_NOTIFY_BOUND_DRIVER)
return NOTIFY_DONE;
devname = dev_name(dev);
if (!had_gpio && !strcmp(devname, GPIO_DEV)) {
tegra_board_pinmux_setup_gpios();
had_gpio = true;
} else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) {
tegra_board_pinmux_setup_pinmux();
had_pinmux = true;
}
if (had_gpio && had_pinmux)
return NOTIFY_STOP_MASK;
else
return NOTIFY_DONE;
}
static struct notifier_block nb = {
.notifier_call = tegra_board_pinmux_bus_notify,
};
static struct platform_device *devices[] = {
&tegra_gpio_device,
&tegra_pinmux_device,
};
void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
struct tegra_board_pinmux_conf *conf_b)
{
confs[0] = conf_a;
confs[1] = conf_b;
bus_register_notifier(&platform_bus_type, &nb);
if (!of_machine_is_compatible("nvidia,tegra20"))
platform_add_devices(devices, ARRAY_SIZE(devices));
}

38
arch/arm/mach-tegra/board-pinmux.h Normal file
View File

@ -0,0 +1,38 @@
/*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_BOARD_PINMUX_H
#define __MACH_TEGRA_BOARD_PINMUX_H
#define GPIO_DEV "tegra-gpio"
#define PINMUX_DEV "tegra-pinmux"
struct tegra_pingroup_config;
struct tegra_gpio_table;
struct tegra_board_pinmux_conf {
struct tegra_pingroup_config *pgs;
int pg_count;
struct tegra_drive_pingroup_config *drives;
int drive_count;
struct tegra_gpio_table *gpios;
int gpio_count;
};
void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
struct tegra_board_pinmux_conf *conf_b);
#endif

128
arch/arm/mach-tegra/board-seaboard-pinmux.c
View File

@ -22,8 +22,8 @@
#include <mach/pinmux-tegra20.h>
#include "gpio-names.h"
#include "board-pinmux.h"
#include "board-seaboard.h"
#include "devices.h"
#define DEFAULT_DRIVE(_name) \
{ \
@ -37,11 +37,11 @@
.slew_falling = TEGRA_SLEW_SLOWEST, \
}
static __initdata struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
DEFAULT_DRIVE(SDIO1),
};
static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
static struct tegra_pingroup_config common_pinmux[] = {
{TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
@ -55,7 +55,6 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
{TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
@ -65,7 +64,6 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
{TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
@ -108,13 +106,8 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
{TEGRA_PINGROUP_LM0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_LM1, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_LPW1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_LSDI, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_LVP0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
@ -122,25 +115,19 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
{TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
@ -160,13 +147,24 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
{TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
};
static __initdata struct tegra_pingroup_config ventana_pinmux[] = {
{TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
static struct tegra_pingroup_config seaboard_pinmux[] = {
{TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
};
static struct tegra_pingroup_config ventana_pinmux[] = {
{TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
@ -181,65 +179,59 @@ static __initdata struct tegra_pingroup_config ventana_pinmux[] = {
{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
};
static struct platform_device *pinmux_devices[] = {
&tegra_gpio_device,
&tegra_pinmux_device,
};
static struct tegra_gpio_table common_gpio_table[] = {
{ .gpio = TEGRA_GPIO_SD2_CD, .enable = true },
{ .gpio = TEGRA_GPIO_SD2_WP, .enable = true },
{ .gpio = TEGRA_GPIO_SD2_POWER, .enable = true },
{ .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true },
};
static struct tegra_gpio_table seaboard_gpio_table[] = {
{ .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true },
{ .gpio = TEGRA_GPIO_POWERKEY, .enable = true },
{ .gpio = TEGRA_GPIO_HP_DET, .enable = true },
{ .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true },
{ .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true },
{ .gpio = TEGRA_GPIO_USB1, .enable = true },
};
static void __init update_pinmux(struct tegra_pingroup_config *newtbl, int size)
{
int i, j;
struct tegra_pingroup_config *new_pingroup, *base_pingroup;
static struct tegra_gpio_table ventana_gpio_table[] = {
/* hp_det */
{ .gpio = TEGRA_GPIO_PW2, .enable = true },
/* int_mic_en */
{ .gpio = TEGRA_GPIO_PX0, .enable = true },
/* ext_mic_en */
{ .gpio = TEGRA_GPIO_PX1, .enable = true },
};
/* Update base seaboard pinmux table with secondary board
* specific pinmux table table.
*/
for (i = 0; i < size; i++) {
new_pingroup = &newtbl[i];
for (j = 0; j < ARRAY_SIZE(seaboard_pinmux); j++) {
base_pingroup = &seaboard_pinmux[j];
if (new_pingroup->pingroup == base_pingroup->pingroup) {
*base_pingroup = *new_pingroup;
break;
}
}
}
static struct tegra_board_pinmux_conf common_conf = {
.pgs = common_pinmux,
.pg_count = ARRAY_SIZE(common_pinmux),
.gpios = common_gpio_table,
.gpio_count = ARRAY_SIZE(common_gpio_table),
};
static struct tegra_board_pinmux_conf seaboard_conf = {
.pgs = seaboard_pinmux,
.pg_count = ARRAY_SIZE(seaboard_pinmux),
.drives = seaboard_drive_pinmux,
.drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
.gpios = seaboard_gpio_table,
.gpio_count = ARRAY_SIZE(seaboard_gpio_table),
};
static struct tegra_board_pinmux_conf ventana_conf = {
.pgs = ventana_pinmux,
.pg_count = ARRAY_SIZE(ventana_pinmux),
.gpios = ventana_gpio_table,
.gpio_count = ARRAY_SIZE(ventana_gpio_table),
};
void seaboard_pinmux_init(void)
{
tegra_board_pinmux_init(&common_conf, &seaboard_conf);
}
void __init seaboard_common_pinmux_init(void)
void ventana_pinmux_init(void)
{
if (!of_machine_is_compatible("nvidia,tegra20"))
platform_add_devices(pinmux_devices,
ARRAY_SIZE(pinmux_devices));
tegra_pinmux_config_table(seaboard_pinmux, ARRAY_SIZE(seaboard_pinmux));
tegra_drive_pinmux_config_table(seaboard_drive_pinmux,
ARRAY_SIZE(seaboard_drive_pinmux));
tegra_gpio_config(common_gpio_table, ARRAY_SIZE(common_gpio_table));
tegra_board_pinmux_init(&common_conf, &ventana_conf);
}
void __init seaboard_pinmux_init(void)
{
seaboard_common_pinmux_init();
}
void __init ventana_pinmux_init(void)
{
update_pinmux(ventana_pinmux, ARRAY_SIZE(ventana_pinmux));
seaboard_common_pinmux_init();
}

26
arch/arm/mach-tegra/board-trimslice-pinmux.c
View File

@ -22,10 +22,10 @@
#include <mach/pinmux-tegra20.h>
#include "gpio-names.h"
#include "board-pinmux.h"
#include "board-trimslice.h"
#include "devices.h"
static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
static struct tegra_pingroup_config trimslice_pinmux[] = {
{TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
@ -106,7 +106,7 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
{TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_PTA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
@ -144,11 +144,6 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
{TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
};
static struct platform_device *pinmux_devices[] = {
&tegra_gpio_device,
&tegra_pinmux_device,
};
static struct tegra_gpio_table gpio_table[] = {
{ .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */
{ .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */
@ -157,11 +152,14 @@ static struct tegra_gpio_table gpio_table[] = {
{ .gpio = TRIMSLICE_GPIO_USB2_RST, .enable = true }, /* USB2 PHY rst */
};
void __init trimslice_pinmux_init(void)
static struct tegra_board_pinmux_conf conf = {
.pgs = trimslice_pinmux,
.pg_count = ARRAY_SIZE(trimslice_pinmux),
.gpios = gpio_table,
.gpio_count = ARRAY_SIZE(gpio_table),
};
void trimslice_pinmux_init(void)
{
if (!of_machine_is_compatible("nvidia,tegra20"))
platform_add_devices(pinmux_devices,
ARRAY_SIZE(pinmux_devices));
tegra_pinmux_config_table(trimslice_pinmux, ARRAY_SIZE(trimslice_pinmux));
tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
tegra_board_pinmux_init(&conf, NULL);
}

1
arch/arm/mach-tegra/pcie.c
View File

@ -37,7 +37,6 @@
#include <asm/sizes.h>
#include <asm/mach/pci.h>
#include <mach/pinmux.h>
#include <mach/iomap.h>
#include <mach/clk.h>
#include <mach/powergate.h>

4
arch/arm/plat-mxc/include/mach/iomux-mx25.h
View File

@ -265,16 +265,20 @@
#define MX25_PAD_CSI_D2__CSI_D2 IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D2__UART5_RXD_MUX IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL)
#define MX25_PAD_CSI_D2__GPIO_1_27 IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D2__CSPI3_MOSI IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D3__CSI_D3 IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D3__GPIO_1_28 IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D3__CSPI3_MISO IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL)
#define MX25_PAD_CSI_D4__CSI_D4 IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D4__UART5_RTS IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL)
#define MX25_PAD_CSI_D4__GPIO_1_29 IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D4__CSPI3_SCLK IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D5__CSI_D5 IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D5__GPIO_1_30 IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D5__CSPI3_RDY IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D6__CSI_D6 IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D6__GPIO_1_31 IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL)

3
arch/arm/plat-omap/include/plat/uncompress.h
View File

@ -179,6 +179,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
/* TI8168 base boards using UART3 */
DEBUG_LL_TI81XX(3, ti8168evm);
/* TI8148 base boards using UART1 */
DEBUG_LL_TI81XX(1, ti8148evm);
} while (0);
}

32
arch/arm/plat-omap/include/plat/usb.h
View File

@ -114,6 +114,7 @@ extern void am35x_musb_reset(void);
extern void am35x_musb_phy_power(u8 on);
extern void am35x_musb_clear_irq(void);
extern void am35x_set_mode(u8 musb_mode);
extern void ti81xx_musb_phy_power(u8 on);
/*
* FIXME correct answer depends on hmc_mode,
@ -273,6 +274,37 @@ static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
#define CONF2_OTGPWRDN (1 << 2)
#define CONF2_DATPOL (1 << 1)
/* TI81XX specific definitions */
#define USBCTRL0 0x620
#define USBSTAT0 0x624
/* TI816X PHY controls bits */
#define TI816X_USBPHY0_NORMAL_MODE (1 << 0)
#define TI816X_USBPHY_REFCLK_OSC (1 << 8)
/* TI814X PHY controls bits */
#define USBPHY_CM_PWRDN (1 << 0)
#define USBPHY_OTG_PWRDN (1 << 1)
#define USBPHY_CHGDET_DIS (1 << 2)
#define USBPHY_CHGDET_RSTRT (1 << 3)
#define USBPHY_SRCONDM (1 << 4)
#define USBPHY_SINKONDP (1 << 5)
#define USBPHY_CHGISINK_EN (1 << 6)
#define USBPHY_CHGVSRC_EN (1 << 7)
#define USBPHY_DMPULLUP (1 << 8)
#define USBPHY_DPPULLUP (1 << 9)
#define USBPHY_CDET_EXTCTL (1 << 10)
#define USBPHY_GPIO_MODE (1 << 12)
#define USBPHY_DPOPBUFCTL (1 << 13)
#define USBPHY_DMOPBUFCTL (1 << 14)
#define USBPHY_DPINPUT (1 << 15)
#define USBPHY_DMINPUT (1 << 16)
#define USBPHY_DPGPIO_PD (1 << 17)
#define USBPHY_DMGPIO_PD (1 << 18)
#define USBPHY_OTGVDET_EN (1 << 19)
#define USBPHY_OTGSESSEND_EN (1 << 20)
#define USBPHY_DATA_POLARITY (1 << 23)
#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
u32 omap1_usb1_init(unsigned nwires);

8
arch/arm/plat-samsung/Kconfig
View File

@ -88,12 +88,20 @@ config S5P_GPIO_DRVSTR
config SAMSUNG_GPIO_EXTRA
int "Number of additional GPIO pins"
default 128 if SAMSUNG_GPIO_EXTRA128
default 64 if SAMSUNG_GPIO_EXTRA64
default 0
help
Use additional GPIO space in addition to the GPIO's the SOC
provides. This allows expanding the GPIO space for use with
GPIO expanders.
config SAMSUNG_GPIO_EXTRA64
bool
config SAMSUNG_GPIO_EXTRA128
bool
config S3C_GPIO_SPACE
int "Space between gpio banks"
default 0