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Merge branch 'pci/misc' 

- Mark expected switch fall-through (Mathieu Malaterre)

  - Use of_node_name_eq() for node name comparisons (Rob Herring)

  - Add ACS and pciehp quirks for HXT SD4800 (Shunyong Yang)

  - Consolidate Rohm Vendor ID definitions (Andy Shevchenko)

  - Use u32 (not __u32) for things not exposed to userspace (Logan
    Gunthorpe)

  - Fix locking semantics of bus and slot reset interfaces (Alex
    Williamson)

  - Update PCIEPORTBUS Kconfig help text (Hou Zhiqiang)

* pci/misc:
  PCI: Update PCIEPORTBUS Kconfig help text
  PCI: Fix "try" semantics of bus and slot reset
  PCI: Clean up usage of __u32 type
  genirq/msi: Clean up usage of __u8/__u16 types
  PCI: Move Rohm Vendor ID to generic list
  PCI: pciehp: Add HXT quirk for Command Completed errata
  PCI: Add ACS quirk for HXT SD4800
  PCI: Add HXT vendor ID
  PCI: Use of_node_name_eq() for node name comparisons
  PCI: Mark expected switch fall-through
This commit is contained in:
Bjorn Helgaas 2019-03-06 15:30:13 -06:00
parent 58a79db481 8f55ed3f55
commit 6d940a71c9
17 changed files with 51 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/dma/pch_dma.c
View File

@ -972,7 +972,6 @@ static void pch_dma_remove(struct pci_dev *pdev)
}
/* PCI Device ID of DMA device */
#define PCI_VENDOR_ID_ROHM 0x10DB
#define PCI_DEVICE_ID_EG20T_PCH_DMA_8CH 0x8810
#define PCI_DEVICE_ID_EG20T_PCH_DMA_4CH 0x8815
#define PCI_DEVICE_ID_ML7213_DMA1_8CH 0x8026

2
drivers/gpio/gpio-ml-ioh.c
View File

@ -31,8 +31,6 @@
#define IOH_IRQ_BASE 0
#define PCI_VENDOR_ID_ROHM 0x10DB
struct ioh_reg_comn {
u32 ien;
u32 istatus;

1
drivers/gpio/gpio-pch.c
View File

@ -437,7 +437,6 @@ static int __maybe_unused pch_gpio_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
#define PCI_VENDOR_ID_ROHM 0x10DB
static const struct pci_device_id pch_gpio_pcidev_id[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },

1
drivers/i2c/busses/i2c-eg20t.c
View File

@ -177,7 +177,6 @@ static wait_queue_head_t pch_event;
static DEFINE_MUTEX(pch_mutex);
/* Definition for ML7213 by LAPIS Semiconductor */
#define PCI_VENDOR_ID_ROHM 0x10DB
#define PCI_DEVICE_ID_ML7213_I2C 0x802D
#define PCI_DEVICE_ID_ML7223_I2C 0x8010
#define PCI_DEVICE_ID_ML7831_I2C 0x8817

1
drivers/misc/pch_phub.c
View File

@ -64,7 +64,6 @@
#define CLKCFG_UARTCLKSEL (1 << 18)
/* Macros for ML7213 */
#define PCI_VENDOR_ID_ROHM 0x10db
#define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A
/* Macros for ML7223 */

7
drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
View File

@ -27,7 +27,6 @@
#define DRV_VERSION "1.01"
const char pch_driver_version[] = DRV_VERSION;
#define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
#define PCH_GBE_MAR_ENTRIES 16
#define PCH_GBE_SHORT_PKT 64
#define DSC_INIT16 0xC000
@ -37,11 +36,9 @@ const char pch_driver_version[] = DRV_VERSION;
#define PCH_GBE_PCI_BAR 1
#define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */
/* Macros for ML7223 */
#define PCI_VENDOR_ID_ROHM 0x10db
#define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
#define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802
/* Macros for ML7831 */
#define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
#define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802
#define PCH_GBE_TX_WEIGHT 64

2
drivers/pci/hotplug/pciehp_hpc.c
View File

@ -920,3 +920,5 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401,
PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);

2
drivers/pci/of.c
View File

@ -113,7 +113,7 @@ struct device_node *of_pci_find_child_device(struct device_node *parent,
* a fake root for all functions of a multi-function
* device we go down them as well.
*/
if (!strcmp(node->name, "multifunc-device")) {
if (of_node_name_eq(node, "multifunc-device")) {
for_each_child_of_node(node, node2) {
if (__of_pci_pci_compare(node2, devfn)) {
of_node_put(node);

4
drivers/pci/pci-driver.c
View File

@ -100,7 +100,7 @@ static ssize_t new_id_store(struct device_driver *driver, const char *buf,
{
struct pci_driver *pdrv = to_pci_driver(driver);
const struct pci_device_id *ids = pdrv->id_table;
__u32 vendor, device, subvendor = PCI_ANY_ID,
u32 vendor, device, subvendor = PCI_ANY_ID,
subdevice = PCI_ANY_ID, class = 0, class_mask = 0;
unsigned long driver_data = 0;
int fields = 0;
@ -168,7 +168,7 @@ static ssize_t remove_id_store(struct device_driver *driver, const char *buf,
{
struct pci_dynid *dynid, *n;
struct pci_driver *pdrv = to_pci_driver(driver);
__u32 vendor, device, subvendor = PCI_ANY_ID,
u32 vendor, device, subvendor = PCI_ANY_ID,
subdevice = PCI_ANY_ID, class = 0, class_mask = 0;
int fields = 0;
size_t retval = -ENODEV;

58
drivers/pci/pci.c
View File

@ -861,7 +861,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
&& !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
need_restore = true;
/* Fall-through: force to D0 */
/* Fall-through - force to D0 */
default:
pmcsr = 0;
break;
@ -2304,7 +2304,7 @@ static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
case PCI_D2:
if (pci_no_d1d2(dev))
break;
/* else: fall through */
/* else, fall through */
default:
target_state = state;
}
@ -5107,39 +5107,42 @@ static int pci_slot_trylock(struct pci_slot *slot)
return 0;
}
/* Save and disable devices from the top of the tree down */
static void pci_bus_save_and_disable(struct pci_bus *bus)
/*
* Save and disable devices from the top of the tree down while holding
* the @dev mutex lock for the entire tree.
*/
static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
{
struct pci_dev *dev;
list_for_each_entry(dev, &bus->devices, bus_list) {
pci_dev_lock(dev);
pci_dev_save_and_disable(dev);
pci_dev_unlock(dev);
if (dev->subordinate)
pci_bus_save_and_disable(dev->subordinate);
pci_bus_save_and_disable_locked(dev->subordinate);
}
}
/*
* Restore devices from top of the tree down - parent bridges need to be
* restored before we can get to subordinate devices.
* Restore devices from top of the tree down while holding @dev mutex lock
* for the entire tree. Parent bridges need to be restored before we can
* get to subordinate devices.
*/
static void pci_bus_restore(struct pci_bus *bus)
static void pci_bus_restore_locked(struct pci_bus *bus)
{
struct pci_dev *dev;
list_for_each_entry(dev, &bus->devices, bus_list) {
pci_dev_lock(dev);
pci_dev_restore(dev);
pci_dev_unlock(dev);
if (dev->subordinate)
pci_bus_restore(dev->subordinate);
pci_bus_restore_locked(dev->subordinate);
}
}
/* Save and disable devices from the top of the tree down */
static void pci_slot_save_and_disable(struct pci_slot *slot)
/*
* Save and disable devices from the top of the tree down while holding
* the @dev mutex lock for the entire tree.
*/
static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
{
struct pci_dev *dev;
@ -5148,26 +5151,25 @@ static void pci_slot_save_and_disable(struct pci_slot *slot)
continue;
pci_dev_save_and_disable(dev);
if (dev->subordinate)
pci_bus_save_and_disable(dev->subordinate);
pci_bus_save_and_disable_locked(dev->subordinate);
}
}
/*
* Restore devices from top of the tree down - parent bridges need to be
* restored before we can get to subordinate devices.
* Restore devices from top of the tree down while holding @dev mutex lock
* for the entire tree. Parent bridges need to be restored before we can
* get to subordinate devices.
*/
static void pci_slot_restore(struct pci_slot *slot)
static void pci_slot_restore_locked(struct pci_slot *slot)
{
struct pci_dev *dev;
list_for_each_entry(dev, &slot->bus->devices, bus_list) {
if (!dev->slot || dev->slot != slot)
continue;
pci_dev_lock(dev);
pci_dev_restore(dev);
pci_dev_unlock(dev);
if (dev->subordinate)
pci_bus_restore(dev->subordinate);
pci_bus_restore_locked(dev->subordinate);
}
}
@ -5226,17 +5228,15 @@ static int __pci_reset_slot(struct pci_slot *slot)
if (rc)
return rc;
pci_slot_save_and_disable(slot);
if (pci_slot_trylock(slot)) {
pci_slot_save_and_disable_locked(slot);
might_sleep();
rc = pci_reset_hotplug_slot(slot->hotplug, 0);
pci_slot_restore_locked(slot);
pci_slot_unlock(slot);
} else
rc = -EAGAIN;
pci_slot_restore(slot);
return rc;
}
@ -5322,17 +5322,15 @@ static int __pci_reset_bus(struct pci_bus *bus)
if (rc)
return rc;
pci_bus_save_and_disable(bus);
if (pci_bus_trylock(bus)) {
pci_bus_save_and_disable_locked(bus);
might_sleep();
rc = pci_bridge_secondary_bus_reset(bus->self);
pci_bus_restore_locked(bus);
pci_bus_unlock(bus);
} else
rc = -EAGAIN;
pci_bus_restore(bus);
return rc;
}

7
drivers/pci/pcie/Kconfig
View File

@ -6,10 +6,9 @@ config PCIEPORTBUS
bool "PCI Express Port Bus support"
depends on PCI
help
This automatically enables PCI Express Port Bus support. Users can
choose Native Hot-Plug support, Advanced Error Reporting support,
Power Management Event support and Virtual Channel support to run
on PCI Express Ports (Root or Switch).
This enables PCI Express Port Bus support. Users can then enable
support for Native Hot-Plug, Advanced Error Reporting, Power
Management Events, and Downstream Port Containment.
#
# Include service Kconfig here

4
drivers/pci/quirks.c
View File

@ -2138,7 +2138,7 @@ static void quirk_netmos(struct pci_dev *dev)
if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
dev->subsystem_device == 0x0299)
return;
/* else: fall through */
/* else, fall through */
case PCI_DEVICE_ID_NETMOS_9735:
case PCI_DEVICE_ID_NETMOS_9745:
case PCI_DEVICE_ID_NETMOS_9845:
@ -4519,6 +4519,8 @@ static const struct pci_dev_acs_enabled {
/* QCOM QDF2xxx root ports */
{ PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
{ PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
/* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
{ PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
/* Intel PCH root ports */
{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },

1
drivers/spi/spi-topcliff-pch.c
View File

@ -92,7 +92,6 @@
#define PCH_MAX_SPBR 1023
/* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
#define PCI_VENDOR_ID_ROHM 0x10DB
#define PCI_DEVICE_ID_ML7213_SPI 0x802c
#define PCI_DEVICE_ID_ML7223_SPI 0x800F
#define PCI_DEVICE_ID_ML7831_SPI 0x8816

2
drivers/tty/serial/pch_uart.c
View File

@ -192,8 +192,6 @@ enum {
#define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
#define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
#define PCI_VENDOR_ID_ROHM 0x10DB
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
#define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */

1
drivers/usb/gadget/udc/pch_udc.c
View File

@ -368,7 +368,6 @@ struct pch_udc_dev {
#define PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC 0x0939
#define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808
#define PCI_VENDOR_ID_ROHM 0x10DB
#define PCI_DEVICE_ID_ML7213_IOH_UDC 0x801D
#define PCI_DEVICE_ID_ML7831_IOH_UDC 0x8808

12
include/linux/msi.h
View File

@ -83,12 +83,12 @@ struct msi_desc {
struct {
u32 masked;
struct {
__u8 is_msix : 1;
__u8 multiple : 3;
__u8 multi_cap : 3;
__u8 maskbit : 1;
__u8 is_64 : 1;
__u16 entry_nr;
u8 is_msix : 1;
u8 multiple : 3;
u8 multi_cap : 3;
u8 maskbit : 1;
u8 is_64 : 1;
u16 entry_nr;
unsigned default_irq;
} msi_attrib;
union {

4
include/linux/pci_ids.h
View File

@ -1140,6 +1140,8 @@
#define PCI_VENDOR_ID_TCONRAD 0x10da
#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508
#define PCI_VENDOR_ID_ROHM 0x10db
#define PCI_VENDOR_ID_NVIDIA 0x10de
#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020
#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028
@ -2573,6 +2575,8 @@
#define PCI_VENDOR_ID_HYGON 0x1d94
#define PCI_VENDOR_ID_HXT 0x1dbf
#define PCI_VENDOR_ID_TEKRAM 0x1de1
#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29