mirror of https://gitee.com/openkylin/linux.git
drm/amd/display: move bw calc code into helpers
[Why] For better readability and reusability [How] Move snippets of BW calculation code into helpers. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Fatemeh Darbehani <Fatemeh.Darbehani@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Yang
Alex Deucher
parent
4bc846908b
commit
6de202373b
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@ -26,8 +26,6 @@
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#include "dccg.h"
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#include "clk_mgr_internal.h"
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#include "dcn20/dcn20_clk_mgr.h"
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#include "dce100/dce_clk_mgr.h"
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#include "reg_helper.h"
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#include "core_types.h"
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@ -2018,15 +2018,16 @@ static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
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}
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#endif
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bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
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bool fast_validate)
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bool dcn20_fast_validate_bw(
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struct dc *dc,
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struct dc_state *context,
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display_e2e_pipe_params_st *pipes,
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int *pipe_split_from,
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int *vlevel_out)
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{
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bool out = false;
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BW_VAL_TRACE_SETUP();
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int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
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int pipe_split_from[MAX_PIPES];
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bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
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bool force_split = false;
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#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
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@ -2034,10 +2035,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
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#endif
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int split_threshold = dc->res_pool->pipe_count / 2;
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bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
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display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
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DC_LOGGER_INIT(dc->ctx->logger);
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BW_VAL_TRACE_COUNT();
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ASSERT(pipes);
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if (!pipes)
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@ -2077,7 +2075,6 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
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&context->res_ctx, pipes);
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if (!pipe_cnt) {
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BW_VAL_TRACE_SKIP(pass);
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out = true;
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goto validate_out;
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}
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@ -2242,101 +2239,128 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
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}
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#endif
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BW_VAL_TRACE_END_VOLTAGE_LEVEL();
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*vlevel_out = vlevel;
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if (fast_validate) {
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BW_VAL_TRACE_SKIP(fast);
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out = true;
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goto validate_out;
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}
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out = true;
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goto validate_out;
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validate_fail:
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out = false;
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validate_out:
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return out;
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}
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void dcn20_calculate_wm(
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struct dc *dc, struct dc_state *context,
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display_e2e_pipe_params_st *pipes,
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int *out_pipe_cnt,
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int *pipe_split_from,
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int vlevel)
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{
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int pipe_cnt, i, pipe_idx;
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for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
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if (!context->res_ctx.pipe_ctx[i].stream)
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continue;
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if (!context->res_ctx.pipe_ctx[i].stream)
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continue;
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pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
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pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
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pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
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pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
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if (pipe_split_from[i] < 0) {
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pipes[pipe_cnt].clks_cfg.dppclk_mhz =
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context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
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if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
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pipes[pipe_cnt].pipe.dest.odm_combine =
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context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
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else
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pipes[pipe_cnt].pipe.dest.odm_combine = 0;
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pipe_idx++;
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} else {
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pipes[pipe_cnt].clks_cfg.dppclk_mhz =
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context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
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if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
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pipes[pipe_cnt].pipe.dest.odm_combine =
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context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
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else
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pipes[pipe_cnt].pipe.dest.odm_combine = 0;
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if (pipe_split_from[i] < 0) {
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pipes[pipe_cnt].clks_cfg.dppclk_mhz =
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context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
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if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
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pipes[pipe_cnt].pipe.dest.odm_combine =
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context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
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else
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pipes[pipe_cnt].pipe.dest.odm_combine = 0;
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pipe_idx++;
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} else {
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pipes[pipe_cnt].clks_cfg.dppclk_mhz =
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context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
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if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
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pipes[pipe_cnt].pipe.dest.odm_combine =
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context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
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else
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pipes[pipe_cnt].pipe.dest.odm_combine = 0;
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}
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if (dc->config.forced_clocks) {
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pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
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pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
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}
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pipe_cnt++;
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}
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if (dc->config.forced_clocks) {
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pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
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pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
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if (pipe_cnt != pipe_idx) {
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if (dc->res_pool->funcs->populate_dml_pipes)
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pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
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&context->res_ctx, pipes);
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else
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pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
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&context->res_ctx, pipes);
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}
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pipe_cnt++;
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}
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if (pipe_cnt != pipe_idx) {
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if (dc->res_pool->funcs->populate_dml_pipes)
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pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
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&context->res_ctx, pipes);
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else
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pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
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&context->res_ctx, pipes);
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}
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*out_pipe_cnt = pipe_cnt;
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pipes[0].clks_cfg.voltage = vlevel;
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pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
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pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
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pipes[0].clks_cfg.voltage = vlevel;
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pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
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pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
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/* only pipe 0 is read for voltage and dcf/soc clocks */
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if (vlevel < 1) {
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pipes[0].clks_cfg.voltage = 1;
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pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
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pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
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}
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context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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/* only pipe 0 is read for voltage and dcf/soc clocks */
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if (vlevel < 1) {
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pipes[0].clks_cfg.voltage = 1;
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pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
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pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
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}
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context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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if (vlevel < 2) {
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pipes[0].clks_cfg.voltage = 2;
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pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
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pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
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}
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context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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if (vlevel < 2) {
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pipes[0].clks_cfg.voltage = 2;
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pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
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pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
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}
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context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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if (vlevel < 3) {
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pipes[0].clks_cfg.voltage = 3;
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pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
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pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
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}
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context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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if (vlevel < 3) {
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pipes[0].clks_cfg.voltage = 3;
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pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
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pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
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}
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context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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pipes[0].clks_cfg.voltage = vlevel;
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pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
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pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
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context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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}
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void dcn20_calculate_dlg_params(
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struct dc *dc, struct dc_state *context,
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display_e2e_pipe_params_st *pipes,
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int pipe_cnt,
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int vlevel)
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{
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int i, pipe_idx;
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pipes[0].clks_cfg.voltage = vlevel;
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pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
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pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
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context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
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/* Writeback MCIF_WB arbitration parameters */
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dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
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@ -2351,7 +2375,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
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!= dm_dram_clock_change_unsupported;
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context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
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BW_VAL_TRACE_END_WATERMARKS();
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for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
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if (!context->res_ctx.pipe_ctx[i].stream)
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|
|
@ -2393,8 +2417,40 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
|
|||
pipes[pipe_idx].pipe);
|
||||
pipe_idx++;
|
||||
}
|
||||
}
|
||||
|
||||
bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
|
||||
bool fast_validate)
|
||||
{
|
||||
bool out = false;
|
||||
|
||||
BW_VAL_TRACE_SETUP();
|
||||
|
||||
int vlevel = 0;
|
||||
int pipe_split_from[MAX_PIPES];
|
||||
int pipe_cnt = 0;
|
||||
display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
|
||||
DC_LOGGER_INIT(dc->ctx->logger);
|
||||
|
||||
BW_VAL_TRACE_COUNT();
|
||||
|
||||
out = dcn20_fast_validate_bw(dc, context, pipes, pipe_split_from, &vlevel);
|
||||
|
||||
if (!out)
|
||||
goto validate_fail;
|
||||
|
||||
BW_VAL_TRACE_END_VOLTAGE_LEVEL();
|
||||
|
||||
if (fast_validate) {
|
||||
BW_VAL_TRACE_SKIP(fast);
|
||||
goto validate_out;
|
||||
}
|
||||
|
||||
dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
|
||||
dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
|
||||
|
||||
BW_VAL_TRACE_END_WATERMARKS();
|
||||
|
||||
out = true;
|
||||
goto validate_out;
|
||||
|
||||
validate_fail:
|
||||
|
|
|
|||
|
|
@ -116,6 +116,17 @@ void dcn20_set_mcif_arb_params(
|
|||
display_e2e_pipe_params_st *pipes,
|
||||
int pipe_cnt);
|
||||
bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);
|
||||
bool dcn20_fast_validate_bw(
|
||||
struct dc *dc,
|
||||
struct dc_state *context,
|
||||
display_e2e_pipe_params_st *pipes,
|
||||
int *pipe_split_from,
|
||||
int *vlevel_out);
|
||||
void dcn20_calculate_dlg_params(
|
||||
struct dc *dc, struct dc_state *context,
|
||||
display_e2e_pipe_params_st *pipes,
|
||||
int pipe_cnt,
|
||||
int vlevel);
|
||||
|
||||
enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
|
||||
enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
|
||||
|
|
|
|||
|
|
@ -64,6 +64,8 @@ enum dentist_divider_range {
|
|||
***************************************************************************************
|
||||
*/
|
||||
|
||||
/* Macros */
|
||||
|
||||
#define TO_CLK_MGR_INTERNAL(clk_mgr)\
|
||||
container_of(clk_mgr, struct clk_mgr_internal, base)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue