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drm/radeon/cik: use hw defaults for TC_CFG registers 

Use the hw power up values rather than 0.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2014-01-13 10:18:03 -05:00
parent 919cf555c0
commit 6dfa09d7c9
1 changed files with 0 additions and 14 deletions
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14
drivers/gpu/drm/radeon/cik.c
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@ -5353,20 +5353,6 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
/* TC cache setup ??? */
WREG32(TC_CFG_L1_LOAD_POLICY0, 0);
WREG32(TC_CFG_L1_LOAD_POLICY1, 0);
WREG32(TC_CFG_L1_STORE_POLICY, 0);
WREG32(TC_CFG_L2_LOAD_POLICY0, 0);
WREG32(TC_CFG_L2_LOAD_POLICY1, 0);
WREG32(TC_CFG_L2_STORE_POLICY0, 0);
WREG32(TC_CFG_L2_STORE_POLICY1, 0);
WREG32(TC_CFG_L2_ATOMIC_POLICY, 0);
WREG32(TC_CFG_L1_VOLATILE, 0);
WREG32(TC_CFG_L2_VOLATILE, 0);
if (rdev->family == CHIP_KAVERI) {
u32 tmp = RREG32(CHUB_CONTROL);
tmp &= ~BYPASS_VM;