mirror of https://gitee.com/openkylin/linux.git
spi/mpc5121: Add SPI master driver for MPC5121 PSC
Signed-off-by: John Rigby <jcrigby@gmail.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Anatolij Gustschin
Grant Likely
parent
2da8cb6af5
commit
6e27388f1b
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@ -248,6 +248,7 @@ struct mpc52xx_psc_fifo {
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u16 tflwfptr; /* PSC + 0x9e */
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};
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#define MPC512x_PSC_FIFO_EOF 0x100
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#define MPC512x_PSC_FIFO_RESET_SLICE 0x80
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#define MPC512x_PSC_FIFO_ENABLE_SLICE 0x01
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#define MPC512x_PSC_FIFO_ENABLE_DMA 0x04
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@ -175,6 +175,13 @@ config SPI_MPC52xx_PSC
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This enables using the Freescale MPC52xx Programmable Serial
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Controller in master SPI mode.
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config SPI_MPC512x_PSC
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tristate "Freescale MPC512x PSC SPI controller"
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depends on SPI_MASTER && PPC_MPC512x
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help
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This enables using the Freescale MPC5121 Programmable Serial
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Controller in SPI master mode.
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config SPI_MPC8xxx
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tristate "Freescale MPC8xxx SPI controller"
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depends on FSL_SOC
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@ -31,6 +31,7 @@ obj-$(CONFIG_SPI_OMAP24XX) += omap2_mcspi.o
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obj-$(CONFIG_SPI_OMAP_100K) += omap_spi_100k.o
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obj-$(CONFIG_SPI_ORION) += orion_spi.o
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obj-$(CONFIG_SPI_PL022) += amba-pl022.o
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obj-$(CONFIG_SPI_MPC512x_PSC) += mpc512x_psc_spi.o
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obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
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obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
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obj-$(CONFIG_SPI_MPC8xxx) += spi_mpc8xxx.o
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@ -0,0 +1,576 @@
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/*
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* MPC512x PSC in SPI mode driver.
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*
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* Copyright (C) 2007,2008 Freescale Semiconductor Inc.
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* Original port from 52xx driver:
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* Hongjun Chen <hong-jun.chen@freescale.com>
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*
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* Fork of mpc52xx_psc_spi.c:
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* Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/of_platform.h>
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#include <linux/workqueue.h>
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#include <linux/completion.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/spi/spi.h>
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#include <linux/fsl_devices.h>
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#include <asm/mpc52xx_psc.h>
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struct mpc512x_psc_spi {
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void (*cs_control)(struct spi_device *spi, bool on);
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u32 sysclk;
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/* driver internal data */
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struct mpc52xx_psc __iomem *psc;
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struct mpc512x_psc_fifo __iomem *fifo;
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unsigned int irq;
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u8 bits_per_word;
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u8 busy;
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u32 mclk;
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u8 eofbyte;
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struct workqueue_struct *workqueue;
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struct work_struct work;
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struct list_head queue;
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spinlock_t lock; /* Message queue lock */
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struct completion done;
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};
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/* controller state */
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struct mpc512x_psc_spi_cs {
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int bits_per_word;
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int speed_hz;
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};
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/* set clock freq, clock ramp, bits per work
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* if t is NULL then reset the values to the default values
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*/
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static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct mpc512x_psc_spi_cs *cs = spi->controller_state;
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cs->speed_hz = (t && t->speed_hz)
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? t->speed_hz : spi->max_speed_hz;
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cs->bits_per_word = (t && t->bits_per_word)
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? t->bits_per_word : spi->bits_per_word;
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cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
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return 0;
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}
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static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
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{
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struct mpc512x_psc_spi_cs *cs = spi->controller_state;
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struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
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struct mpc52xx_psc __iomem *psc = mps->psc;
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u32 sicr;
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u32 ccr;
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u16 bclkdiv;
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sicr = in_be32(&psc->sicr);
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/* Set clock phase and polarity */
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if (spi->mode & SPI_CPHA)
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sicr |= 0x00001000;
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else
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sicr &= ~0x00001000;
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if (spi->mode & SPI_CPOL)
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sicr |= 0x00002000;
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else
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sicr &= ~0x00002000;
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if (spi->mode & SPI_LSB_FIRST)
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sicr |= 0x10000000;
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else
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sicr &= ~0x10000000;
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out_be32(&psc->sicr, sicr);
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ccr = in_be32(&psc->ccr);
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ccr &= 0xFF000000;
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if (cs->speed_hz)
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bclkdiv = (mps->mclk / cs->speed_hz) - 1;
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else
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bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
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ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
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out_be32(&psc->ccr, ccr);
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mps->bits_per_word = cs->bits_per_word;
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if (mps->cs_control)
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mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
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}
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static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
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{
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struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
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if (mps->cs_control)
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mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
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}
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/* extract and scale size field in txsz or rxsz */
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#define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
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#define EOFBYTE 1
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static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
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struct mpc52xx_psc __iomem *psc = mps->psc;
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struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
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size_t len = t->len;
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u8 *tx_buf = (u8 *)t->tx_buf;
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u8 *rx_buf = (u8 *)t->rx_buf;
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if (!tx_buf && !rx_buf && t->len)
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return -EINVAL;
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/* Zero MR2 */
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in_8(&psc->mode);
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out_8(&psc->mode, 0x0);
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while (len) {
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int count;
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int i;
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u8 data;
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size_t fifosz;
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int rxcount;
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/*
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* The number of bytes that can be sent at a time
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* depends on the fifo size.
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*/
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fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
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count = min(fifosz, len);
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for (i = count; i > 0; i--) {
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data = tx_buf ? *tx_buf++ : 0;
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if (len == EOFBYTE)
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setbits32(&fifo->txcmd, MPC512x_PSC_FIFO_EOF);
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out_8(&fifo->txdata_8, data);
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len--;
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}
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INIT_COMPLETION(mps->done);
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/* interrupt on tx fifo empty */
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out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
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out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
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/* enable transmiter/receiver */
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out_8(&psc->command,
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MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
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wait_for_completion(&mps->done);
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mdelay(1);
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/* rx fifo should have count bytes in it */
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rxcount = in_be32(&fifo->rxcnt);
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if (rxcount != count)
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mdelay(1);
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rxcount = in_be32(&fifo->rxcnt);
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if (rxcount != count) {
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dev_warn(&spi->dev, "expected %d bytes in rx fifo "
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"but got %d\n", count, rxcount);
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}
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rxcount = min(rxcount, count);
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for (i = rxcount; i > 0; i--) {
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data = in_8(&fifo->rxdata_8);
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if (rx_buf)
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*rx_buf++ = data;
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}
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while (in_be32(&fifo->rxcnt)) {
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in_8(&fifo->rxdata_8);
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}
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out_8(&psc->command,
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MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
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}
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/* disable transmiter/receiver and fifo interrupt */
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out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
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out_be32(&fifo->tximr, 0);
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return 0;
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}
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static void mpc512x_psc_spi_work(struct work_struct *work)
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{
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struct mpc512x_psc_spi *mps = container_of(work,
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struct mpc512x_psc_spi,
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work);
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spin_lock_irq(&mps->lock);
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mps->busy = 1;
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while (!list_empty(&mps->queue)) {
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struct spi_message *m;
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struct spi_device *spi;
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struct spi_transfer *t = NULL;
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unsigned cs_change;
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int status;
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m = container_of(mps->queue.next, struct spi_message, queue);
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list_del_init(&m->queue);
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spin_unlock_irq(&mps->lock);
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spi = m->spi;
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cs_change = 1;
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status = 0;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->bits_per_word || t->speed_hz) {
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status = mpc512x_psc_spi_transfer_setup(spi, t);
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if (status < 0)
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break;
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}
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if (cs_change)
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mpc512x_psc_spi_activate_cs(spi);
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cs_change = t->cs_change;
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status = mpc512x_psc_spi_transfer_rxtx(spi, t);
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if (status)
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break;
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m->actual_length += t->len;
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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if (cs_change)
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mpc512x_psc_spi_deactivate_cs(spi);
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}
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m->status = status;
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m->complete(m->context);
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if (status || !cs_change)
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mpc512x_psc_spi_deactivate_cs(spi);
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mpc512x_psc_spi_transfer_setup(spi, NULL);
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spin_lock_irq(&mps->lock);
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}
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mps->busy = 0;
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spin_unlock_irq(&mps->lock);
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}
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static int mpc512x_psc_spi_setup(struct spi_device *spi)
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{
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struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
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struct mpc512x_psc_spi_cs *cs = spi->controller_state;
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unsigned long flags;
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if (spi->bits_per_word % 8)
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return -EINVAL;
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if (!cs) {
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cs = kzalloc(sizeof *cs, GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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spi->controller_state = cs;
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}
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cs->bits_per_word = spi->bits_per_word;
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cs->speed_hz = spi->max_speed_hz;
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spin_lock_irqsave(&mps->lock, flags);
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if (!mps->busy)
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mpc512x_psc_spi_deactivate_cs(spi);
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spin_unlock_irqrestore(&mps->lock, flags);
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return 0;
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}
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static int mpc512x_psc_spi_transfer(struct spi_device *spi,
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struct spi_message *m)
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{
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struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
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unsigned long flags;
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m->actual_length = 0;
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m->status = -EINPROGRESS;
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spin_lock_irqsave(&mps->lock, flags);
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list_add_tail(&m->queue, &mps->queue);
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queue_work(mps->workqueue, &mps->work);
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spin_unlock_irqrestore(&mps->lock, flags);
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return 0;
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}
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static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
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{
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kfree(spi->controller_state);
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}
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static int mpc512x_psc_spi_port_config(struct spi_master *master,
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struct mpc512x_psc_spi *mps)
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{
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struct mpc52xx_psc __iomem *psc = mps->psc;
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struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
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struct clk *spiclk;
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int ret = 0;
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char name[32];
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u32 sicr;
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u32 ccr;
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u16 bclkdiv;
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sprintf(name, "psc%d_mclk", master->bus_num);
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spiclk = clk_get(&master->dev, name);
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clk_enable(spiclk);
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mps->mclk = clk_get_rate(spiclk);
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clk_put(spiclk);
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/* Reset the PSC into a known state */
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out_8(&psc->command, MPC52xx_PSC_RST_RX);
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out_8(&psc->command, MPC52xx_PSC_RST_TX);
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out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
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/* Disable psc interrupts all useful interrupts are in fifo */
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out_be16(&psc->isr_imr.imr, 0);
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/* Disable fifo interrupts, will be enabled later */
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out_be32(&fifo->tximr, 0);
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out_be32(&fifo->rximr, 0);
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/* Setup fifo slice address and size */
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/*out_be32(&fifo->txsz, 0x0fe00004);*/
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/*out_be32(&fifo->rxsz, 0x0ff00004);*/
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sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */
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0x00800000 | /* GenClk = 1 -- internal clk */
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0x00008000 | /* SPI = 1 */
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0x00004000 | /* MSTR = 1 -- SPI master */
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0x00000800; /* UseEOF = 1 -- SS low until EOF */
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out_be32(&psc->sicr, sicr);
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ccr = in_be32(&psc->ccr);
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ccr &= 0xFF000000;
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bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
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ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
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out_be32(&psc->ccr, ccr);
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/* Set 2ms DTL delay */
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out_8(&psc->ctur, 0x00);
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out_8(&psc->ctlr, 0x82);
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/* we don't use the alarms */
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out_be32(&fifo->rxalarm, 0xfff);
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out_be32(&fifo->txalarm, 0);
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/* Enable FIFO slices for Rx/Tx */
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out_be32(&fifo->rxcmd,
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MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
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out_be32(&fifo->txcmd,
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MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
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mps->bits_per_word = 8;
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return ret;
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}
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static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
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{
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struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
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struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
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/* clear interrupt and wake up the work queue */
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if (in_be32(&fifo->txisr) &
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in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
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out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
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out_be32(&fifo->tximr, 0);
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complete(&mps->done);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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/* bus_num is used only for the case dev->platform_data == NULL */
|
||||
static int __init mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
|
||||
u32 size, unsigned int irq,
|
||||
s16 bus_num)
|
||||
{
|
||||
struct fsl_spi_platform_data *pdata = dev->platform_data;
|
||||
struct mpc512x_psc_spi *mps;
|
||||
struct spi_master *master;
|
||||
int ret;
|
||||
void *tempp;
|
||||
|
||||
master = spi_alloc_master(dev, sizeof *mps);
|
||||
if (master == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
dev_set_drvdata(dev, master);
|
||||
mps = spi_master_get_devdata(master);
|
||||
mps->irq = irq;
|
||||
|
||||
if (pdata == NULL) {
|
||||
dev_err(dev, "probe called without platform data, no "
|
||||
"cs_control function will be called\n");
|
||||
mps->cs_control = NULL;
|
||||
mps->sysclk = 0;
|
||||
master->bus_num = bus_num;
|
||||
master->num_chipselect = 255;
|
||||
} else {
|
||||
mps->cs_control = pdata->cs_control;
|
||||
mps->sysclk = pdata->sysclk;
|
||||
master->bus_num = pdata->bus_num;
|
||||
master->num_chipselect = pdata->max_chipselect;
|
||||
}
|
||||
|
||||
master->setup = mpc512x_psc_spi_setup;
|
||||
master->transfer = mpc512x_psc_spi_transfer;
|
||||
master->cleanup = mpc512x_psc_spi_cleanup;
|
||||
|
||||
tempp = ioremap(regaddr, size);
|
||||
if (!tempp) {
|
||||
dev_err(dev, "could not ioremap I/O port range\n");
|
||||
ret = -EFAULT;
|
||||
goto free_master;
|
||||
}
|
||||
mps->psc = tempp;
|
||||
mps->fifo =
|
||||
(struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
|
||||
|
||||
ret = request_irq(mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
|
||||
"mpc512x-psc-spi", mps);
|
||||
if (ret)
|
||||
goto free_master;
|
||||
|
||||
ret = mpc512x_psc_spi_port_config(master, mps);
|
||||
if (ret < 0)
|
||||
goto free_irq;
|
||||
|
||||
spin_lock_init(&mps->lock);
|
||||
init_completion(&mps->done);
|
||||
INIT_WORK(&mps->work, mpc512x_psc_spi_work);
|
||||
INIT_LIST_HEAD(&mps->queue);
|
||||
|
||||
mps->workqueue =
|
||||
create_singlethread_workqueue(dev_name(master->dev.parent));
|
||||
if (mps->workqueue == NULL) {
|
||||
ret = -EBUSY;
|
||||
goto free_irq;
|
||||
}
|
||||
|
||||
ret = spi_register_master(master);
|
||||
if (ret < 0)
|
||||
goto unreg_master;
|
||||
|
||||
return ret;
|
||||
|
||||
unreg_master:
|
||||
destroy_workqueue(mps->workqueue);
|
||||
free_irq:
|
||||
free_irq(mps->irq, mps);
|
||||
free_master:
|
||||
if (mps->psc)
|
||||
iounmap(mps->psc);
|
||||
spi_master_put(master);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __exit mpc512x_psc_spi_do_remove(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
|
||||
|
||||
flush_workqueue(mps->workqueue);
|
||||
destroy_workqueue(mps->workqueue);
|
||||
spi_unregister_master(master);
|
||||
free_irq(mps->irq, mps);
|
||||
if (mps->psc)
|
||||
iounmap(mps->psc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init mpc512x_psc_spi_of_probe(struct of_device *op,
|
||||
const struct of_device_id *match)
|
||||
{
|
||||
const u32 *regaddr_p;
|
||||
u64 regaddr64, size64;
|
||||
s16 id = -1;
|
||||
|
||||
regaddr_p = of_get_address(op->node, 0, &size64, NULL);
|
||||
if (!regaddr_p) {
|
||||
dev_err(&op->dev, "Invalid PSC address\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
regaddr64 = of_translate_address(op->node, regaddr_p);
|
||||
|
||||
/* get PSC id (0..11, used by port_config) */
|
||||
if (op->dev.platform_data == NULL) {
|
||||
const u32 *psc_nump;
|
||||
|
||||
psc_nump = of_get_property(op->node, "cell-index", NULL);
|
||||
if (!psc_nump || *psc_nump > 11) {
|
||||
dev_err(&op->dev, "mpc512x_psc_spi: Device node %s "
|
||||
"has invalid cell-index property\n",
|
||||
op->node->full_name);
|
||||
return -EINVAL;
|
||||
}
|
||||
id = *psc_nump;
|
||||
}
|
||||
|
||||
return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
|
||||
irq_of_parse_and_map(op->node, 0), id);
|
||||
}
|
||||
|
||||
static int __exit mpc512x_psc_spi_of_remove(struct of_device *op)
|
||||
{
|
||||
return mpc512x_psc_spi_do_remove(&op->dev);
|
||||
}
|
||||
|
||||
static struct of_device_id mpc512x_psc_spi_of_match[] = {
|
||||
{ .compatible = "fsl,mpc5121-psc-spi", },
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
|
||||
|
||||
static struct of_platform_driver mpc512x_psc_spi_of_driver = {
|
||||
.match_table = mpc512x_psc_spi_of_match,
|
||||
.probe = mpc512x_psc_spi_of_probe,
|
||||
.remove = __exit_p(mpc512x_psc_spi_of_remove),
|
||||
.driver = {
|
||||
.name = "mpc512x-psc-spi",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init mpc512x_psc_spi_init(void)
|
||||
{
|
||||
return of_register_platform_driver(&mpc512x_psc_spi_of_driver);
|
||||
}
|
||||
module_init(mpc512x_psc_spi_init);
|
||||
|
||||
static void __exit mpc512x_psc_spi_exit(void)
|
||||
{
|
||||
of_unregister_platform_driver(&mpc512x_psc_spi_of_driver);
|
||||
}
|
||||
module_exit(mpc512x_psc_spi_exit);
|
||||
|
||||
MODULE_AUTHOR("John Rigby");
|
||||
MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue